[Intel-gfx] [PATCH] drm/i915/dp: only use training pattern 3 on platforms that support it

[Ville Syrjälä]

On Wed, Oct 29, 2014 at 11:03:26AM +0200, Jani Nikula wrote:
> Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
> doesn't support DP3 we should even bother trying to use it.
> 
> This regression has been introduced in
> 
> commit 06ea66b6bb445043dc25a9626254d5c130093199
> Author: Todd Previte <tprevite at gmail.com>
> Date:   Mon Jan 20 10:19:39 2014 -0700
> 
>     drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable
> devices
> 
> Reported-by: Dave Airlie <airlied at redhat.com>
> Reference: http://mid.gmane.org/1414566170-9868-1-git-send-email-airlied@gmail.com
> Cc: Todd Previte <tprevite at gmail.com>
> Cc: stable at vger.kernel.org (3.15+)
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 82e47dafe293..47e9d71c14a3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3945,9 +3945,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  		}
>  	}
>  
> -	/* Training Pattern 3 support */
> +	/* Training Pattern 3 support, both source and sink */
>  	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
> -	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
> +	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
> +	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {

Yep that looks better. Additonally we could drop the
'link_bw == DP_LINK_BW_5_4' check from intel_dp_complete_link_train()
and just rely on use_tps3 since pattern 3 is mandatory for HBR2
capable sinks, and so they really should advertise DP_TPS3_SUPPORTED.
But on the other hand I don't see any harm in keeping the current
logic there.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

>  		intel_dp->use_tps3 = true;
>  		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
>  	} else
> -- 
> 2.1.1

-- 
Ville Syrjälä
Intel OTC