[Intel-gfx] [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers
Rodrigo Vivi
rodrigo.vivi at gmail.com
Wed Oct 29 22:18:49 CET 2014
On Thu, Oct 16, 2014 at 10:52 AM, <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> CHV adds a bunch of new registers for primary plane size/position and
> pipe blender setup. Initialize all those registers to avoid nasty
> surprises. PRIMSIZE is especially important as without programming it
> the outout will be garbled whenever the primary plane size would not
> match what the BIOS set up.
>
> Also program the sprite constant alpha register to disable the constant
> alpha blending factor. This applies to vlv as well as chv.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 2 ++
> 3 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 46cfbc7..c5c3b70 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4270,9 +4270,11 @@ enum punit_power_well {
> #define DISPPLANE_NO_LINE_DOUBLE 0
> #define DISPPLANE_STEREO_POLARITY_FIRST 0
> #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
> -#define DISPPLANE_ROTATE_180 (1<<15)
> +#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
> +#define DISPPLANE_ROTATE_180 (1<<15)
> #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
> #define DISPPLANE_TILED (1<<10)
> +#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
> #define _DSPAADDR 0x70184
> #define _DSPASTRIDE 0x70188
> #define _DSPAPOS 0x7018C /* reserved */
> @@ -4293,6 +4295,24 @@ enum punit_power_well {
> #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
> #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
>
> +/* CHV pipe B blender and primary plane */
> +#define _CHV_BLEND_A 0x60a00
> +#define CHV_BLEND_LEGACY (0<<30)
> +#define CHV_BLEND_ANDROID (1<<30)
> +#define CHV_BLEND_MPO (2<<30)
> +#define CHV_BLEND_MASK (3<<30)
> +#define _CHV_CANVAS_A 0x60a04
> +#define _PRIMPOS_A 0x60a08
> +#define _PRIMSIZE_A 0x60a0c
> +#define _PRIMCNSTALPHA_A 0x60a10
> +#define PRIM_CONST_ALPHA_ENABLE (1<<31)
> +
> +#define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A)
> +#define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A)
> +#define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A)
> +#define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A)
> +#define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A)
> +
> /* Display/Sprite base address macros */
> #define DISP_BASEADDR_MASK (0xfffff000)
> #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
> @@ -4494,6 +4514,7 @@ enum punit_power_well {
> #define SP_FORMAT_RGBA1010102 (9<<26)
> #define SP_FORMAT_RGBX8888 (0xe<<26)
> #define SP_FORMAT_RGBA8888 (0xf<<26)
> +#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
> #define SP_SOURCE_KEY (1<<22)
> #define SP_YUV_BYTE_ORDER_MASK (3<<16)
> #define SP_YUV_ORDER_YUYV (0<<16)
> @@ -4502,6 +4523,7 @@ enum punit_power_well {
> #define SP_YUV_ORDER_VYUY (3<<16)
> #define SP_ROTATE_180 (1<<15)
> #define SP_TILED (1<<10)
> +#define SP_MIRROR (1<<8) /* CHV pipe B */
> #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
> @@ -4512,6 +4534,7 @@ enum punit_power_well {
> #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
> #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
> #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
> +#define SP_CONST_ALPHA_ENABLE (1<<31)
I don't believe this is on the right place...
> #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
>
> #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 18b493f..d901961 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2443,6 +2443,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> ((intel_crtc->config.pipe_src_h - 1) << 16) |
> (intel_crtc->config.pipe_src_w - 1));
> I915_WRITE(DSPPOS(plane), 0);
> + } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> + I915_WRITE(PRIMSIZE(plane),
> + ((intel_crtc->config.pipe_src_h - 1) << 16) |
> + (intel_crtc->config.pipe_src_w - 1));
> + I915_WRITE(PRIMPOS(plane), 0);
> + I915_WRITE(PRIMCNSTALPHA(plane), 0);
> }
>
> switch (fb->pixel_format) {
> @@ -4848,6 +4854,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>
> intel_set_pipe_timings(intel_crtc);
>
> + if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> + I915_WRITE(CHV_CANVAS(pipe), 0);
> + }
> +
> i9xx_set_pipeconf(intel_crtc);
>
> intel_crtc->active = true;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 2c060ad..a452819 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -438,6 +438,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> else
> I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
>
> + I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
> +
Is this also valid for byt?
> I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
> I915_WRITE(SPCNTR(pipe, plane), sprctl);
> I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
> --
> 2.0.4
>
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rest looks good so if those explained/fixed feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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