[Intel-gfx] [PATCH 06/10] drm/i915: Rearrange RPS frequency calculation
Chris Wilson
chris at chris-wilson.co.uk
Tue Sep 2 15:57:41 CEST 2014
The goal is to refactor the Cherryview special casing to only be in a
single location. To do so we need to compute the desired adjustment and
then tweak it for Cherryview. This has the minor side-effect of making
sure we set adj to 0 if we directly update the target frequency.
Ensuring that the RPS constants are correct for Cherryview is outside
the scope of this function
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 60ca89986499..586625b78cbb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1420,21 +1420,20 @@ static void gen6_pm_rps_work(struct work_struct *work)
mutex_lock(&dev_priv->rps.hw_lock);
adj = dev_priv->rps.last_adj;
+ new_delay = dev_priv->rps.cur_freq;
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
if (adj > 0)
adj *= 2;
- else {
- /* CHV needs even encode values */
- adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
- }
- new_delay = dev_priv->rps.cur_freq + adj;
-
+ else
+ adj = 1;
/*
* For better performance, jump directly
* to RPe if we're below it.
*/
- if (new_delay < dev_priv->rps.efficient_freq)
+ if (new_delay < dev_priv->rps.efficient_freq - adj) {
new_delay = dev_priv->rps.efficient_freq;
+ adj = 0;
+ }
} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
new_delay = dev_priv->rps.efficient_freq;
@@ -1446,15 +1445,17 @@ static void gen6_pm_rps_work(struct work_struct *work)
} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
if (adj < 0)
adj *= 2;
- else {
- /* CHV needs even encode values */
- adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
- }
- new_delay = dev_priv->rps.cur_freq + adj;
+ else
+ adj = -1;
} else { /* unknown event */
- new_delay = dev_priv->rps.cur_freq;
+ adj = 0;
}
+ /* CHV needs even encode values */
+ if (IS_CHERRYVIEW(dev_priv->dev))
+ adj <<= 1;
+ new_delay += adj;
+
/* sysfs frequency interfaces may have snuck in while servicing the
* interrupt
*/
--
2.1.0
More information about the Intel-gfx
mailing list