[Intel-gfx] [PATCH 00/89] Basic Skylake enabling

[Damien Lespiau]

Hi,

This series implements basic enabling for Skylake (SKL), bringing us to roughly
feature parity with earlier platforms.

Skylake (SKL) is the latest Intel® Processor containing Intel® HD Graphics.

The major GPU hardware features include:
- Gen9 Intel® HD Graphics graphics
- The addition of a 3rd display plane (not concurrent with the cursor)
- Five HDMI/DP/eDP display ports

The bulk of the series is on the display side where things have changed quite a
bit with new DPLL, watermarks and display planes code. The remaining of the
patches deals with incremental changes in various features of the device: RC6,
forcewake engines, power wells, execlists, ...

Big thanks to everyone who contributed for their tireless efforts.

-- 
Damien

Daisy Sun (1):
  drm/i915/skl: SKL FBC enablement

Damien Lespiau (49):
  drm/i915/skl: Add the Skylake PCI ids
  drm/i915/skl: Add an IS_GEN9() define
  drm/i915/skl: Fence registers on SKL are the same as SNB
  drm/i915/skl: Provide a placeholder for init_clock_gating()
  drm/i915/skl: Use gen8_ring_dispatch_execbuffer() on GEN9
  drm/i915/skl: Skylake shares the interrupt logic with Broadwell
  drm/i915/skl: Framebuffers need to be aligned to 256Kb on Skylake
  drm/i915/skl: Implement thew new update_plane() for primary planes
  drm/i915/skl: Don't create a VGA connector on Skylake
  drm/i915/skl: Don't try to read out the PCH transcoder state if not
    present
  drm/i915/skl: Program the DDI buffer translation tables
  drm/i915/skl: Add support for DP voltage swings and pre-emphasis
  drm/i915/skl: Skylake doesn't need the DP AUX clock divider programmed
  drm/i915/skl: Skylake moves AUX_CTL from PCH to CPU
  drm/i915/skl: Add the additional graphics stolen sizes
  drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+
  drm/i915/skl: Implement the get_aux_clock_divider() DP vfunc
  drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylake
  drm/i915/skl: Initialize PPGTT like gen8
  drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMP
  drm/i915/skl: report the same INSTDONE registers as gen8
  drm/i915/skl: Report the PDP regs as in gen8
  drm/i915/skl: SKL shares the same underrun interrupt as BDW
  drm/i915/skl: Adjust the display engine interrupts
  drm/i915/skl: Implement WaDisableSDEUnitClockGating:skl
  drm/i915/skl: Implement Wa4x4STCOptimizationDisable:skl
  drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl
  drm/i915/skl: Skylake has 2 "sprite" planes per pipe
  drm/i915/skl: Implement drm_plane vfuncs
  drm/i915/skl: Adjust assert_sprites_disabled()
  drm/i915/skl: Introduce a I915_MAX_PLANES macro
  drm/i915/skl: Introduce intel_num_planes()
  drm/i915/skl: Move gen9 pm initialization into its own branch
  drm/i915/skl: Add DDB allocation management structures
  drm/i915/skl: Allocate DDB portions for display planes
  drm/i915/skl: Program the DDB allocation
  drm/i915: Rewrite ABS_DIFF() in a safer manner
  drm/i915/skl: Provide skl-specific pll hw state cross-checking
  drm/i915/skl: Implement queue_flip
  drm/i915/skl: Store the new WM state at the very end of the update
  drm/i915: Introduce a for_each_plane() macro
  drm/i915/skl: Flush the WM configuration
  drm/i915/skl: Read back the DDB allocation hw state
  drm/i915/skl: Augment the latency debugfs files for SKL
  drm/i915/skl: Expose skl_ddb_get_hw_state()
  drm/i915/skl: Add a debugfs file to dump the DDB allocation
  drm/i915/skl: Check the DDB state at modeset
  drm/i915/skl: Retrieve the frequency limits
  drm/i915/skl: Disable contexts if execlists aren't enabled

Imre Deak (1):
  drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+

Jesse Barnes (4):
  drm/i915/skl: fetch, enable/disable pfit as needed
  drm/i915/skl: add turbo support
  drm/i915: only reset media, blt, and render engines on GPU hangs
  drm/i915/skl: AUX irqs have moved

Michael H. Nguyen (1):
  drm/i915/skl: Add Gen9 LRC size

Pradeep Bhat (5):
  drm/i915/skl: Read the Memory Latency Values for WM computation
  drm/i915/skl: Register definitions and macros for SKL Watermark regs
  drm/i915/skl: Definition of SKL WM param structs for pipe/plane
  drm/i915/skl: SKL Watermark Computation
  drm/i915/skl: Read the pipe WM HW state

Robert Beckett (1):
  drm/i915/skl: i915_swizzle_info gen9 fix

Satheeshakrishna M (20):
  drm/i915/skl: Add an IS_SKYLAKE macro
  drm/i915/skl: SKL pipe misc programming
  drm/i915/skl: vfuncs for skl eld and global resource
  drm/i915/skl: SKL backlight enabling
  drm/i915/skl: Restore pipe B/C interrupts
  drm/i915/skl: Sunrise Point PCH detection
  drm/i915/skl: Register definitions for SKL Clocks
  drm/i915/skl: Structure/enum definitions for SKL clocks
  drm/i915/skl: CD clock back calculation for SKL
  drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock
  drm/i915/skl: Query DPLL attached to port on SKL
  drm/i915/skl: Define shared DPLLs for Skylake
  drm/i915/skl: Adjust the port PLL selection code
  drm/i915/skl: Always use DPLL0 for eDP
  drm/i915/skl: Implementation of SKL DPLL programming
  drm/i915/skl: Adding power domains for AUX controllers
  drm/i915/skl: Register definition for SKL power well
  drm/i915/skl: Implementation of SKL display power well support
  drm/i915/skl: Enable/disable power well for aux transaction
  drm/i915/skl: Enabling MISC IO power well

Vandana Kannan (3):
  drm/i915/gen9: Add 2us read latency to WM level
  drm/i915/gen9: Disable WM if corresponding latency is 0
  drm/i915/skl: Apply eDP WA only for gen < 9

Zhe Wang (4):
  drm/i915/skl: Gen9 Forcewake
  drm/i915/skl: Enable Gen9 RC6
  drm/i915/skl: Gen9 multi-engine forcewake
  drm/i915: Gen9 shadowed registers

 arch/x86/kernel/early-quirks.c          |   23 +
 drivers/gpu/drm/i915/i915_debugfs.c     |  123 ++-
 drivers/gpu/drm/i915/i915_dma.c         |    2 +-
 drivers/gpu/drm/i915/i915_drv.c         |   26 +-
 drivers/gpu/drm/i915/i915_drv.h         |  117 ++-
 drivers/gpu/drm/i915/i915_gem.c         |    1 +
 drivers/gpu/drm/i915/i915_gem_context.c |    2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |   20 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |    3 +
 drivers/gpu/drm/i915/i915_irq.c         |   54 +-
 drivers/gpu/drm/i915/i915_reg.h         |  359 +++++++-
 drivers/gpu/drm/i915/intel_ddi.c        |  629 +++++++++++++-
 drivers/gpu/drm/i915/intel_display.c    |  358 +++++++-
 drivers/gpu/drm/i915/intel_dp.c         |  136 ++-
 drivers/gpu/drm/i915/intel_drv.h        |   28 +-
 drivers/gpu/drm/i915/intel_lrc.c        |    8 +-
 drivers/gpu/drm/i915/intel_panel.c      |    2 +-
 drivers/gpu/drm/i915/intel_pm.c         | 1385 +++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |    4 +-
 drivers/gpu/drm/i915/intel_sprite.c     |  206 ++++-
 drivers/gpu/drm/i915/intel_uncore.c     |  324 +++++++-
 include/drm/i915_pciids.h               |   17 +
 22 files changed, 3651 insertions(+), 176 deletions(-)

-- 
1.8.3.1