[Intel-gfx] [PATCH v3] drm/i915/bdw: BDW Software Turbo

Paulo Zanoni przanoni at gmail.com
Thu Sep 4 22:59:37 CEST 2014


2014-08-28 6:10 GMT-03:00 Chris Wilson <chris at chris-wilson.co.uk>:
> On Wed, Aug 27, 2014 at 08:57:56PM +0200, Daniel Vetter wrote:
>> On Thu, Aug 14, 2014 at 12:37:53PM -0700, Jesse Barnes wrote:
>> > On Mon, 11 Aug 2014 23:33:57 +0200
>> > Daniel Vetter <daniel at ffwll.ch> wrote:
>> >
>> > > On Mon, Aug 11, 2014 at 11:08:38AM -0700, Daisy Sun wrote:
>> > > > BDW supports GT C0 residency reporting in constant time unit. Driver
>> > > > calculates GT utilization based on C0 residency and adjusts RP
>> > > > frequency up/down accordingly. For offscreen workload specificly,
>> > > > set frequency to RP0.
>> > > >
>> > > > Offscreen task is not restricted by frame rate, it can be
>> > > > executed as soon as possible. Transcoding and serilized workload
>> > > > between CPU and GPU both need high GT performance, RP0 is a good
>> > > > option in this case. RC6 will kick in to compensate power
>> > > > consumption when GT is not active.
>> > > >
>> > > > v2: Rebase on recent drm-intel-nightly
>> > > > v3: Add flip timerout monitor, when no flip is deteced within
>> > > > 100ms, set frequency to RP0.
>> > >
>> > > Ok, let's make this really clear:
>> > >
>> > > If you wire this into the flip handling in any way, I will not merge your
>> > > patch. The timer should be fully independant and tie into the gpu
>> > > busy/idle handling we already have.
>> >
>> > Sounds like Daisy won't be able to spend any more time on this either.
>> >
>> > So we're left with this patch, which does improve things for most
>> > cases, or no patch, which leaves things universally bad.
>> >
>> > Unless someone wants to pick up the additional work and testing of
>> > using a timer scheme, making sure we don't have needless wakeups, and
>> > generally improve power/perf across even more cases than this patch.
>>
>> I'm taking this as an ack from you and pulled the patch into dinq.
>
> Maybe also a nak from me for the bad design and poor integration with
> the existing RPS infrastructue?

And I just concluded this is the first bad commit for
igt/pm_rpm/gem-execbuf. You have to run the test a few times (less
than 10 is enough), then check for a highly polluted dmesg. A simple
"git revert" is still possible on -nightly, and apparently fixes the
issue for me.

I am also right now trying to write a patch that fixes the bug, so I
guess we can avoid the revert if we want.

[   68.892465] ------------[ cut here ]------------
[   68.892547] WARNING: CPU: 1 PID: 142 at
drivers/gpu/drm/i915/intel_uncore.c:47
assert_device_not_suspended.isra.8+0x43/0x50 [i915]()
[   68.892552] Device suspended
[   68.892556] Modules linked in: snd_hda_codec_hdmi intel_rapl
x86_pkg_temp_thermal intel_powerclamp serio_raw efivars btusb iwlmvm
iwlwifi mei_me snd_hda_intel snd_hda_controller mei snd_hda_codec
snd_hwdep snd_pcm_oss snd_mixer_oss snd_pcm snd_timer int3403_thermal
i2c_designware_platform i2c_designware_core acpi_pad fuse nls_utf8
nls_cp437 vfat fat sd_mod ahci libahci i915 drm_kms_helper sdhci_pci
drm e1000e sdhci_acpi sdhci
[   68.892646] CPU: 1 PID: 142 Comm: kworker/u16:2 Tainted: G        W
     3.17.0-rc2.1409041708pz+ #1073
[   68.892652] Hardware name: Intel Corporation Broadwell Client
platform/Wilson Beach SDS, BIOS BDW-E2R1.86C.0072.R03.1405072127
05/07/2014
[   68.892683] Workqueue: i915 gen8_set_frequency_RP0 [i915]
[   68.892690]  0000000000000009 ffff880240557c50 ffffffff816f6d23
ffff880240557c98
[   68.892702]  ffff880240557c88 ffffffff8107b368 ffff8800377e0000
000000000000a008
[   68.892713]  000000000000a008 ffff8800377e0068 ffff8802406b5000
ffff880240557ce8
[   68.892724] Call Trace:
[   68.892743]  [<ffffffff816f6d23>] dump_stack+0x4d/0x66
[   68.892755]  [<ffffffff8107b368>] warn_slowpath_common+0x78/0xa0
[   68.892764]  [<ffffffff8107b3d7>] warn_slowpath_fmt+0x47/0x50
[   68.892816]  [<ffffffffa0129aa3>]
assert_device_not_suspended.isra.8+0x43/0x50 [i915]
[   68.892863]  [<ffffffffa012da15>] gen8_write32+0x35/0x180 [i915]
[   68.892894]  [<ffffffffa00eeb39>] gen6_set_rps+0x219/0x430 [i915]
[   68.892924]  [<ffffffffa00eee7b>] gen8_set_frequency_RP0+0x2b/0x40 [i915]
[   68.892935]  [<ffffffff81094a4a>] process_one_work+0x1da/0x510
[   68.892944]  [<ffffffff810949ea>] ? process_one_work+0x17a/0x510
[   68.892957]  [<ffffffff8109504b>] worker_thread+0x6b/0x4a0
[   68.892967]  [<ffffffff81094fe0>] ? rescuer_thread+0x260/0x260
[   68.892978]  [<ffffffff81099d30>] kthread+0x100/0x120
[   68.892991]  [<ffffffff81099c30>] ? kthread_create_on_node+0x230/0x230
[   68.893002]  [<ffffffff81700fac>] ret_from_fork+0x7c/0xb0
[   68.893013]  [<ffffffff81099c30>] ? kthread_create_on_node+0x230/0x230
[   68.893019] ---[ end trace 999107c7a7ea5be9 ]---
[   68.893027] ------------[ cut here ]------------

> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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-- 
Paulo Zanoni



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