[Intel-gfx] [PATCH] drm/i915: Evict CS TLBs between batches

[Chris Wilson]

On Sun, Sep 07, 2014 at 09:08:31AM +0100, Chris Wilson wrote:
> Running igt, I was encountering the invalid TLB bug on my 845g, despite
> that it was using the CS workaround. Examining the w/a buffer in the
> error state, showed that the copy from the user batch into the
> workaround itself was suffering from the invalid TLB bug (the first
> cacheline was broken with the first two words reversed). Time to try a
> fresh approach. This extends the workaround to write into each page of
> our scratch buffer in order to overflow the TLB and evict the invalid
> entries. This could be refined to only do so after we update the GTT,
> but for simplicity, we do it before each batch.

This seems to hold up under scruting, so far at least. So I am more
convinced that this effectively does the right thing.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre