[Intel-gfx] [PATCH v2 13/16] drm/i915: Fix DVO 2x clock enable on 830M

[Daniel Vetter]

On Fri, Sep 05, 2014 at 09:52:42PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The spec says:
> "For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
> GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
> (DPLL VCO Enable) and Bit 30 (2X Clock Enable) must be set to “1” in
> both the DPLL A Control Register (06014h-06017h) and DPLL B Control
> Register (06018h-0601Bh)."
> 
> The pipe A and B force quirks take care of DPLL_VCO_ENABLE, so we
> just need a bit of special care to handle DPLL_DVO_2X_MODE.
> 
> v2: Recompute num_dvo_pipes on the spot, use PIPE_A/PIPE_B instead
>     of pipe/!pipe for the register offsets in disable (Daniel)
>     Add a comment about the ordering in enable and another one
>     about filtering out the DVO 2x bit in state readout
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 53 +++++++++++++++++++++++++++++++++---
>  1 file changed, 49 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 842a5e1..6d6214a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1612,6 +1612,18 @@ static void chv_enable_pll(struct intel_crtc *crtc)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +static int intel_num_dvo_pipes(struct drm_device *dev)
> +{
> +	struct intel_crtc *crtc;
> +	int count = 0;
> +
> +	for_each_intel_crtc(dev, crtc)
> +		count += crtc->active &&
> +			intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
> +
> +	return count;
> +}
> +
>  static void i9xx_enable_pll(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> @@ -1628,7 +1640,18 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>  	if (IS_MOBILE(dev) && !IS_I830(dev))
>  		assert_panel_unlocked(dev_priv, crtc->pipe);
>  
> -	I915_WRITE(reg, dpll);
> +	/* Enable DVO 2x clock on both PLLs if necessary */
> +	if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
> +		/*
> +		 * It appears to be important that we don't enable this
> +		 * for the current pipe before otherwise configuring the
> +		 * PLL. No idea how this should be handled if multiple
> +		 * DVO outputs are enabled simultaneosly.
> +		 */
> +		dpll |= DPLL_DVO_2X_MODE;
> +		I915_WRITE(DPLL(!crtc->pipe),
> +			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
> +	}
>  
>  	/* Wait for the clocks to stabilize. */
>  	POSTING_READ(reg);
> @@ -1667,8 +1690,22 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>   *
>   * Note!  This is for pre-ILK only.
>   */
> -static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void i9xx_disable_pll(struct intel_crtc *crtc)
>  {
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum pipe pipe = crtc->pipe;
> +
> +	/* Disable DVO 2x clock on both PLLs if necessary */
> +	if (IS_I830(dev) &&
> +	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
> +	    intel_num_dvo_pipes(dev) == 1) {
> +		I915_WRITE(DPLL(PIPE_B),
> +			   I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
> +		I915_WRITE(DPLL(PIPE_A),
> +			   I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
> +	}
> +
>  	/* Don't disable pipe or pipe PLLs if needed */
>  	if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
>  	    (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
> @@ -4940,7 +4977,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
>  		else if (IS_VALLEYVIEW(dev))
>  			vlv_disable_pll(dev_priv, pipe);
>  		else
> -			i9xx_disable_pll(dev_priv, pipe);
> +			i9xx_disable_pll(intel_crtc);
>  	}
>  
>  	if (!IS_GEN2(dev))
> @@ -5944,7 +5981,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  			dpll |= PLL_P2_DIVIDE_BY_4;
>  	}
>  
> -	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
> +	if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
>  		dpll |= DPLL_DVO_2X_MODE;
>  
>  	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
> @@ -6450,6 +6487,14 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	}
>  	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
>  	if (!IS_VALLEYVIEW(dev)) {
> +		/*
> +		 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
> +		 * on 830. Filter it out here so that we don't
> +		 * report errors due to that.
> +		 */
> +		if (IS_I830(dev))
> +			pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
> +
>  		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
>  		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
>  	} else {
> -- 
> 1.8.5.5
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch