[Intel-gfx] [PATCH] drm/i915: HSW always use GGTT selector for secure batches

[Daniel Vetter]

On Wed, Sep 10, 2014 at 03:00:03PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 10, 2014 at 12:21:43PM +0100, Chris Wilson wrote:
> > On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote:
> > > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> > > the security bit (i.e. only privileged batches were allowed to run from
> > > ggtt). From Haswell onwards, you are able to select the security bit
> > 
> > ggtt). For Haswell only, you are able to select the security bit

Rectified.

> > > separate from the address space - and we always requested to use ppgtt.
> > > This breaks the golden render state batch execution with full-ppgtt as
> > > that is only present in the global GTT and more generally any secure
> > > batch that is not colocated in the ppgtt and ggtt. So we need to
> > > disable the use of the ppgtt selector bit for secure batches, or else we
> > > hang immediately upon boot and thence after every GPU reset...
> > > 
> > > v2: Only HSW differentiates between secure dispatch and ggtt, so simply
> > > ignore the differentiation and always use secure==ggtt.
> > > 
> > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch