[Intel-gfx] [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA

[Keith Packard]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> commit d21d781466785c317131a8a57606925867265dc8
> Author: Daniel Vetter <daniel.vetter at ffwll.ch>
> Date:   Tue Feb 22 18:31:44 2011 +0100
>
>     Fix relaxed tiling on gen2

This one matches libdrm in using 16 for the tile height alignment on
gen2.

> Try enabling relaxed fencing again.

> No. The clearest requirement is that the ddx (or other display server)
> must treat incoming surfaces as tainted and validate them to be sure
> that they work with its code paths. If it can't we have a choice of
> either rejecting them outright, or staging them.

If there's a stricter alignment requirement, then we must fix both the
2D driver and libdrm. Otherwise, the user's session will simply crash at
startup.

However, I still see absolutely no evidence that gen2 requires tile
alignment to 32 rows, or that gen3+ requires tile alignment to 16
rows in any software configuration at all.

-- 
keith.packard at intel.com
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