[Intel-gfx] [PATCH 73/89] drm/i915/skl: Enabling MISC IO power well

[Imre Deak]

On Thu, 2014-09-04 at 12:27 +0100, Damien Lespiau wrote:
> From: Satheeshakrishna M <satheeshakrishna.m at intel.com>
> 
> Earlier it was thought that MISC IO is always ON power well.
> But it doesn't looks like the case as confirmed by the HW team.
> Adding code to enable/disable MISC IO power well.
> 
> v2: Use power well data for comparison (Imre)
> 
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m at intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 853b596..5425d85 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7204,6 +7204,21 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
>  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
>  	BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (                       \
> +	BIT(POWER_DOMAIN_AUX_A) |                       \
> +	BIT(POWER_DOMAIN_AUX_B) |                       \
> +	BIT(POWER_DOMAIN_AUX_C) |                       \
> +	BIT(POWER_DOMAIN_AUX_D) |                       \
> +	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
> +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
> +	BIT(POWER_DOMAIN_AUDIO) |                       \
> +	BIT(POWER_DOMAIN_INIT))

From the bspec page "Skylake Sequences to Initialize Display":
"""
Most display engine functions will not operate while display is not
initialized. Only basic PCI, I/O, and MMIO register read/write
operations are supported when display is not initialized.
"""

And for the display to be initialized we need power well#1 and the misc
power well. Based on this we need the misc power well (and power well#1)
for all domains, so simply:
#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS POWER_DOMAIN_MASK


>  #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
>  	(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
>  	SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
> @@ -7241,6 +7256,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  	case SKL_DISP_PW_DDI_B:
>  	case SKL_DISP_PW_DDI_C:
>  	case SKL_DISP_PW_DDI_D:
> +	case SKL_DISP_PW_MISC_IO:
>  		break;
>  	default:
>  		return;
> @@ -8211,6 +8227,12 @@ static struct i915_power_well skl_power_wells[] = {
>  		.ops = &skl_power_well_ops,
>  		.data = SKL_DISP_PW_DDI_D,
>  	},
> +	{
> +		.name = "MISC IO power well",
> +		.domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.data = SKL_DISP_PW_MISC_IO,
> +	}

Based on the above bspec page, the misc power well needs to be enabled
before any other power wells, so it needs to be the first entry.

Optionally this patch could be squashed into 71/89.

With the above changes:
Reviewed-by: Imre Deak <imre.deak at intel.com>

>  };
>  
>  #define set_power_wells(power_domains, __power_wells) ({		\

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