[Intel-gfx] [PATCH 3/8] drm/i915: Partition the fence registers for vgpu in i915 driver

[Jike Song]

From: Yu Zhang <yu.c.zhang at intel.com>

In XenGT, the fence registers are partitioned by multiple vgpu instances
in different VMs. Routine i915_gem_load() is modified to reset the
num_fence_regs, when the driver detects it's runing in a VM. And the
allocated fence numbers is provided in PV INFO page structure.

Signed-off-by: Yu Zhang <yu.c.zhang at intel.com>
Signed-off-by: Jike Song <jike.song at intel.com>
Signed-off-by: Eddie Dong <eddie.dong at intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a5351d..3471f15 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5038,6 +5038,10 @@ i915_gem_load(struct drm_device *dev)
 	else
 		dev_priv->num_fence_regs = 8;
 
+	if (intel_vgpu_active(dev))
+		dev_priv->num_fence_regs =
+				I915_READ(vgt_info_off(avail_rs.fence_num));
+
 	/* Initialize fence registers to zero */
 	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 	i915_gem_restore_fences(dev);
-- 
1.9.1