[Intel-gfx] [PATCH 60/89] drm/i915/skl: CD clock back calculation for SKL

[Paulo Zanoni]

2014-09-04 8:27 GMT-03:00 Damien Lespiau <damien.lespiau at intel.com>:
> From: Satheeshakrishna M <satheeshakrishna.m at intel.com>
>
> Determine programmed cd clock for SKL.
>
> v2: Fix the LCPLL1 enable warning logic
>
> v3: Rebase over the hsw pll rework.
>
> v4: Rebase on top of the per-platform split (Damien)
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m at intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 76 +++++++++++++++++++++++++++++++++++-----
>  1 file changed, 67 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ba1103f..e7a5428 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1260,6 +1260,55 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>         }
>  }
>
> +static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
> +{
> +       uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> +       uint32_t cdctl = I915_READ(CDCLK_CTL);
> +       uint32_t linkrate;
> +
> +       if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
> +               WARN(1, "LCPLL1 not enabled\n");
> +               return 24000; /* 24MHz is the cd freq with NSSC ref */
> +       }
> +
> +       if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> +               return 540000;
> +
> +       linkrate = (I915_READ(DPLL_CTRL1) &
> +                   DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> +
> +       if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
> +           linkrate == DPLL_CRTL1_LINK_RATE_1080) {
> +               /* vco 8640 */
> +               switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> +               case CDCLK_FREQ_450_432:
> +                       return 432000;
> +               case CDCLK_FREQ_337_308:
> +                       return 308570;
> +               case CDCLK_FREQ_675_617:
> +                       return 617140;
> +                       break;

This is the only line with a "break" after a return :)


> +               default:
> +                       WARN(1, "Unknown cd freq selection\n");
> +               }
> +       } else {
> +               /* vco 8100 */
> +               switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> +               case CDCLK_FREQ_450_432:
> +                       return 450000;
> +               case CDCLK_FREQ_337_308:
> +                       return 337500;
> +               case CDCLK_FREQ_675_617:
> +                       return 675000;
> +               default:
> +                       WARN(1, "Unknown cd freq selection\n");
> +               }
> +       }
> +
> +       /* error case, do as if DPLL0 isn't enabled */
> +       return 24000;
> +}
> +
>  static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  {
>         uint32_t lcpll = I915_READ(LCPLL_CTL);
> @@ -1301,6 +1350,9 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  {
>         struct drm_device *dev = dev_priv->dev;
>
> +       if (IS_SKYLAKE(dev))
> +               return skl_get_cdclk_freq(dev_priv);
> +

I hope someone will replace this with a "switch (INTEL_INFO(gen))"
before Gen 15 :)

With or without changes: Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>


>         if (IS_BROADWELL(dev))
>                 return bdw_get_cdclk_freq(dev_priv);
>
> @@ -1369,19 +1421,25 @@ void intel_ddi_pll_init(struct drm_device *dev)
>
>         hsw_shared_dplls_init(dev_priv);
>
> -       /* The LCPLL register should be turned on by the BIOS. For now let's
> -        * just check its state and print errors in case something is wrong.
> -        * Don't even try to turn it on.
> -        */
> -
>         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
>                       intel_ddi_get_cdclk_freq(dev_priv));
>
> -       if (val & LCPLL_CD_SOURCE_FCLK)
> -               DRM_ERROR("CDCLK source is not LCPLL\n");
> +       if (IS_SKYLAKE(dev)) {
> +               if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> +                       DRM_ERROR("LCPLL1 is disabled\n");
> +       } else {
> +               /*
> +                * The LCPLL register should be turned on by the BIOS. For now
> +                * let's just check its state and print errors in case
> +                * something is wrong.  Don't even try to turn it on.
> +                */
> +
> +               if (val & LCPLL_CD_SOURCE_FCLK)
> +                       DRM_ERROR("CDCLK source is not LCPLL\n");
>
> -       if (val & LCPLL_PLL_DISABLE)
> -               DRM_ERROR("LCPLL is disabled\n");
> +               if (val & LCPLL_PLL_DISABLE)
> +                       DRM_ERROR("LCPLL is disabled\n");
> +       }
>  }
>
>  void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
> --
> 1.8.3.1
>
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-- 
Paulo Zanoni