[Intel-gfx] [PATCH 1/4] drm/i915: PSR: organize setup function.

Paulo Zanoni przanoni at gmail.com
Tue Sep 23 22:59:08 CEST 2014


2014-09-16 20:19 GMT-03:00 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> psr_enabled is already by itself a setup once so let's put the W/As there and
> rename old setup once to setup_vsc.

Yeah, I prefer the new way too.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d9091dc7..271788e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1755,10 +1755,8 @@ static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
>         POSTING_READ(ctl_reg);
>  }
>
> -static void intel_edp_psr_setup(struct intel_dp *intel_dp)
> +static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
>  {
> -       struct drm_device *dev = intel_dp_to_dev(intel_dp);
> -       struct drm_i915_private *dev_priv = dev->dev_private;
>         struct edp_vsc_psr psr_vsc;
>
>         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> @@ -1768,10 +1766,6 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp)
>         psr_vsc.sdp_header.HB2 = 0x2;
>         psr_vsc.sdp_header.HB3 = 0x8;
>         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
> -
> -       /* Avoid continuous PSR exit by masking memup and hpd */
> -       I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> -                  EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>  }
>
>  static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
> @@ -1924,8 +1918,11 @@ void intel_edp_psr_enable(struct intel_dp *intel_dp)
>
>         dev_priv->psr.busy_frontbuffer_bits = 0;
>
> -       /* Setup PSR once */
> -       intel_edp_psr_setup(intel_dp);
> +       intel_edp_psr_setup_vsc(intel_dp);
> +
> +       /* Avoid continuous PSR exit by masking memup and hpd */
> +       I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> +                  EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>
>         if (intel_edp_psr_match_conditions(intel_dp))
>                 dev_priv->psr.enabled = intel_dp;
> --
> 1.9.3
>
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-- 
Paulo Zanoni



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