[Intel-gfx] [PATCH 54/89] drm/i915/skl: Enable Gen9 RC6

[Bob Wang]

On 09/22/2014 02:15 PM, Mika Kuoppala wrote:
> Damien Lespiau <damien.lespiau at intel.com> writes:
>
>> From: Zhe Wang <zhe1.wang at intel.com>
>>
>> Configure and enable RC6 for Gen9.
>>
>> v2: Rebase on top of BDW rc6 support (Damien)
>>
>> Signed-off-by: Zhe Wang <zhe1.wang at intel.com>
>> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 52 ++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 51 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index fdf297f..74a8519 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4332,6 +4332,13 @@ static void gen8_disable_rps_interrupts(struct drm_device *dev)
>>   	}
>>   }
>>   
>> +static void gen9_disable_rps(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> +	I915_WRITE(GEN6_RC_CONTROL, 0);
>> +}
>> +
>>   static void gen6_disable_rps_interrupts(struct drm_device *dev)
>>   {
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>> @@ -4579,6 +4586,45 @@ void bdw_software_turbo(struct drm_device *dev)
>>   			&current_time, &current_c0);
>>   }
>>   
>> +static void gen9_enable_rps(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	struct intel_engine_cs *ring;
>> +	uint32_t rc6_mask = 0;
>> +	int unused;
>> +
>> +	/* 1a: Software RC state - RC0 */
>> +	I915_WRITE(GEN6_RC_STATE, 0);
>> +
>> +	/* 1b: Get forcewake during program sequence. Although the driver
>> +	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
>> +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
>> +
>> +	/* 2a: Disable RC states. */
>> +	I915_WRITE(GEN6_RC_CONTROL, 0);
>> +
>> +	/* 2b: Program RC6 thresholds.*/
>> +	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> 40 << 16
>
>> +	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> +	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> +	for_each_ring(ring, dev_priv, unused)
>> +		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
>> +	I915_WRITE(GEN6_RC_SLEEP, 0);
>> +	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> 50000 50ms/125ms per EI
>
>> +
>> +	/* 3a: Enable RC6 */
>> +	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
>> +		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>> +	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>> +			"on" : "off");
>> +	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>> +				   GEN6_RC_CTL_EI_MODE(1) |
>> +				   rc6_mask);
>> +
>> +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>> +
>> +}
>> +
>>   static void gen8_enable_rps(struct drm_device *dev)
>>   {
>>   	struct drm_i915_private *dev_priv = dev->dev_private;
>> @@ -6158,7 +6204,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
>>   		intel_suspend_gt_powersave(dev);
>>   
>>   		mutex_lock(&dev_priv->rps.hw_lock);
>> -		if (IS_CHERRYVIEW(dev))
>> +		if (INTEL_INFO(dev)->gen >= 9)
>> +			gen9_disable_rps(dev);
>> +		else if (IS_CHERRYVIEW(dev))
>>   			cherryview_disable_rps(dev);
>>   		else if (IS_VALLEYVIEW(dev))
>>   			valleyview_disable_rps(dev);
>> @@ -6184,6 +6232,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>>   		cherryview_enable_rps(dev);
>>   	} else if (IS_VALLEYVIEW(dev)) {
>>   		valleyview_enable_rps(dev);
>> +	} else if (INTEL_INFO(dev)->gen >= 9) {
>> +		gen9_enable_rps(dev);
>>   	} else if (IS_BROADWELL(dev)) {
>>   		gen8_enable_rps(dev);
>>   		__gen6_update_ring_freq(dev);
>> -- 
>> 1.8.3.1
> I couldn't find out if those values suggested are newer than the values
> in this patch. We need to visit this are when we are wiser.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>
The new values are from power performance study on more recent 
platforms. So we decided to start with those as initial version.

We will definitely revisit these numbers and update if there are 
different numbers recommended from architecture team for Gen9.
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