[Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

[Runyan, Arthur J]

>> > So did you verify that the register really is a transcoder register?
>> > Eg. set PIPE_MULT(A) to >1x and use pipe A to drive the EDP transcoder.
>>
>> I did not verify. This change was done based on the fact that the
>> register does not exist in the VPG HTML version of the BPEC for
>> Transcoder_EDP, only TRANS_MULT_A, _B, and _C are defined.
>>
>> Do we have an SI contact that can confirm?
>
>Cc:ing Art.
>
>Art, the confusion here is whether PIPE_MULT is a transcoder register
>or a pipe register. BSpec seems to be telling us that it's a transcoder
>register but the confusion comes from the fact that the EDP transcoder
>doesn't have this register. My theory is that it is a transcoder register,
>but since pixel repeat isn't needed for eDP the register isn't present
>(or relevant) in the EDP transcoder. Can you clarify this?
>
>Although in this case it would be very easy to test this theory on
>actual hardware as I previously suggested.

You are correct.  It's transcoder based.  It only gets used in HDMI/DVI modes, so EDP doesn't get one.  Broadwell was able to properly rename transcoder stuff, so these became TRANS_MULT.