[Intel-gfx] [PATCH] drm/i915: Pin tiled objects for L-shaped configs

[Chris Wilson]

On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 749ab485569e..03c675a4476e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>  			}
>  			break;
>  		}
> +
> +		/* check for L-shaped memory aka modified enhanced addressing */
> +		if (IS_GEN4(dev)) {
> +			uint32_t ddc2 = I915_READ(DCC2);
> +
> +			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
> +				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
> +		}
> +
>  		if (dcc == 0xffffffff) {
>  			DRM_ERROR("Couldn't read from MCHBAR.  "
>  				  "Disabling tiling.\n");

I resurrected my dual-channel evenly loaded gm45 and to my surprise
found it reporting a L-shaped memory layout.

Perhaps the if ((ddc2 & DISABLE) == 0) is inverted or is not the truly
magic bit?

ickle at x200s $ sudo cat /sys/kernel/debug/dri/0/i915_swizzle_info
bit6 swizzle for X-tiling = bit9/bit10/bit11
bit6 swizzle for Y-tiling = bit9/bit11
DDC = 0x000f0002
DDC2 = 0x00000010
C0DRB3 = 0x0000
C1DRB3 = 0x0000
L-shaped memory detected
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre