[Intel-gfx] [PATCH 1/6] drm/i915: Don't use staged config for VLV cdclk calculations

[Daniel Vetter]

On Thu, Apr 02, 2015 at 02:47:56PM +0300, Ander Conselvan de Oliveira wrote:
> -static void valleyview_modeset_global_pipes(struct drm_device *dev,
> +static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
>  					    unsigned *prepare_pipes)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_i915_private *dev_priv = to_i915(state->dev);
>  	struct intel_crtc *intel_crtc;
> -	int max_pixclk = intel_mode_max_pixclk(dev_priv);
> +	int max_pixclk = intel_mode_max_pixclk(state);
> +
> +	if (max_pixclk < 0)
> +		return max_pixclk;
>  
>  	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
>  	    dev_priv->vlv_cdclk_freq)

We need to move the current cdclk_freq into the global state like the
shared pll state. But that's for another patch series, can you please make
a note about it to make sure we don't forget?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch