[Intel-gfx] [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor

[shuang.he at intel.com]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
Task id: 6139
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -5              272/272              267/272
ILK                                  302/302              302/302
SNB                                  303/303              303/303
IVB                                  338/338              338/338
BYT                 -1              287/287              286/287
HSW                                  361/361              361/361
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt at gem_fence_thrash@bo-write-verify-threaded-none      PASS(5)      FAIL(1)PASS(1)
*PNV  igt at gem_fence_thrash@bo-write-verify-x      PASS(2)      FAIL(1)PASS(1)
*PNV  igt at gem_fence_thrash@bo-write-verify-y      PASS(3)      FAIL(1)PASS(1)
 PNV  igt at gem_tiled_pread_pwrite      FAIL(3)PASS(12)      FAIL(1)PASS(1)
 PNV  igt at gem_userptr_blits@coherency-sync      CRASH(5)PASS(9)      CRASH(1)PASS(1)
*BYT  igt at gem_exec_bad_domains@conflicting-write-domain      PASS(21)      FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'