[Intel-gfx] [PATCH 15/49] drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround

[Imre Deak]

On ke, 2015-04-08 at 14:38 +0100, Nick Hoath wrote:
> On 08/04/2015 14:10, Deak, Imre wrote:
> > On ke, 2015-04-08 at 14:04 +0100, Nick Hoath wrote:
> >> On 17/03/2015 09:39, Imre Deak wrote:
> >>> From: Ben Widawsky <benjamin.widawsky at intel.com>
> >>>
> >>> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> >>> Signed-off-by: Imre Deak <imre.deak at intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/i915_reg.h | 1 +
> >>>    drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> >>>    2 files changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 3369a11..b7ba061 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells {
> >>>    #define GEN8_UCGCTL6				0x9430
> >>>    #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
> >>>    #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
> >>> +#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
> >>>
> >>>    #define GEN6_GFXPAUSE				0xA000
> >>>    #define GEN6_RPNSWREQ				0xA008
> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >>> index d5dd0b3..52d3c02 100644
> >>> --- a/drivers/gpu/drm/i915/intel_pm.c
> >>> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >>> @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
> >>>    	/*
> >>>    	 * FIXME:
> >>>    	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
> >>> +	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> 
> Shouldn't this WA therefore have a check for 3x6 around it?

Yes, and that's the reason for the above FIXME:. Once we know which
steppings are not-3x6, or have a way to retrieve this information we can
revisit this (see Jeff's EU slice info patchset). Atm Bspec lists all
BXT devices having a 3x6 config.

--Imre