[Intel-gfx] [PATCH 0/7] drm/i915: CHV DPIO power gating stuff

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

This series implementes DPIO lane power gating for CHV. In addition it
also removes the hack that links both common lane power wells together
so each one can be individually power gated.

There's also some stuff to deal with the DPIO_PHY_CONTROL register
corruption, which is a prerequisite for the actual power gating features
since they will need to frob that register.

I also tossed in the PHY lane stagger patch which has been sitting
around in my trees approximately forever.

And finally I went ahead and cleaned up some of the mess with the CHV
power well definitions which were added before I knew just how the
Punit power well stuff changed from VLV.

This series needs Clint's interpair skew issue fix [1] as otherwise
some lingering link training issues will become worse.

The series (and Clin't fix) is available in a git repo here:
git://github.com/vsyrjala/linux.git chv_dpio_powergating

[1] http://lists.freedesktop.org/archives/intel-gfx/2015-April/064266.html

Ville Syrjälä (7):
  drm/i915: Implement chv display PHY lane stagger setup
  drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
  Revert "drm/i915: Hack to tie both common lanes together on chv"
  drm/i915: Use the default 600ns LDO programming sequence delay
  drm/i915: Only wait for required lanes in vlv_wait_port_ready()
  drm/i915: Implement PHY lane power gating for CHV
  drm/i915: Throw out WIP CHV power well definitions

 drivers/gpu/drm/i915/i915_drv.h         |   2 +
 drivers/gpu/drm/i915/i915_reg.h         |  28 ++++-
 drivers/gpu/drm/i915/intel_display.c    |  10 +-
 drivers/gpu/drm/i915/intel_dp.c         |  47 ++++++-
 drivers/gpu/drm/i915/intel_drv.h        |   5 +-
 drivers/gpu/drm/i915/intel_hdmi.c       |  44 ++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 210 +++++++++++++++-----------------
 7 files changed, 218 insertions(+), 128 deletions(-)

-- 
2.0.5