[Intel-gfx] [PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq

[Ville Syrjälä]

On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
> From: Vandana Kannan <vandana.kannan at intel.com>
> 
> Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
> platforms as required. Needed by the next patch.
> 
> Signed-off-by: Vandana Kannan <vandana.kannan at intel.com>
> Signed-off-by: A.Sunil Kamath <sunil.kamath at intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
>  2 files changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 52e5f18..1b2a294 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1659,7 +1659,7 @@ struct drm_i915_private {
>  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
> -	unsigned int vlv_cdclk_freq;
> +	unsigned int cdclk_freq;
>  	unsigned int hpll_freq;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e54e948..b91862e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> +	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> -			 dev_priv->vlv_cdclk_freq);
> +			 dev_priv->cdclk_freq);
>  
>  	/*
>  	 * Program the gmbus_freq based on the cdclk frequency.
>  	 * BSpec erroneously claims we should aim for 4MHz, but
>  	 * in fact 1MHz is the correct frequency.
>  	 */
> -	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
> +	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +					!= dev_priv->cdclk_freq);
>  
>  	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
>  		cmd = 2;
> @@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 val, cmd;
>  
> -	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
> +	WARN_ON(dev_priv->display.get_display_clock_speed(dev)
> +						!= dev_priv->cdclk_freq);
>  
>  	switch (cdclk) {
>  	case 333333:
> @@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  
>  	if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
> -	    dev_priv->vlv_cdclk_freq)
> +	    dev_priv->cdclk_freq)
>  		return;
>  
>  	/* disable/enable all currently active pipes while we change cdclk */
> @@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
>  	else
>  		default_credits = PFI_CREDIT(8);
>  
> -	if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
> +	if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
>  		/* CHV suggested value is 31 or 63 */
>  		if (IS_CHERRYVIEW(dev_priv))
>  			credits = PFI_CREDIT_31;
> @@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
>  	int max_pixclk = intel_mode_max_pixclk(dev_priv);
>  	int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>  
> -	if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> +	if (req_cdclk != dev_priv->cdclk_freq) {
>  		/*
>  		 * FIXME: We can end up here with all power domains off, yet
>  		 * with a CDCLK frequency other than the minimum. To account
> -- 
> 2.1.0
> 
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-- 
Ville Syrjälä
Intel OTC