[Intel-gfx] [PATCH xf86-video-intel 2/3] sna/gen8: Reduce CHV VS URB entries to 640

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

According to BSpec the max number of VS URB entries for CHV is 640.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 src/sna/gen8_render.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/sna/gen8_render.c b/src/sna/gen8_render.c
index ebabb2e..8ea40e2 100644
--- a/src/sna/gen8_render.c
+++ b/src/sna/gen8_render.c
@@ -205,6 +205,11 @@ static const struct blendinfo {
 #define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
 #define OUT_VERTEX_F(v) vertex_emit(sna, v)
 
+inline static bool is_chv(struct sna *sna)
+{
+	return sna->kgem.gen == 0101;
+}
+
 static inline bool too_large(int width, int height)
 {
 	return width > GEN8_MAX_SIZE || height > GEN8_MAX_SIZE;
@@ -462,7 +467,7 @@ gen8_emit_urb(struct sna *sna)
 {
 	/* num of VS entries must be divisible by 8 if size < 9 */
 	OUT_BATCH(GEN8_3DSTATE_URB_VS | (2 - 2));
-	OUT_BATCH(960 << URB_ENTRY_NUMBER_SHIFT |
+	OUT_BATCH((is_chv(sna) ? 640 : 960) << URB_ENTRY_NUMBER_SHIFT |
 		  (2 - 1) << URB_ENTRY_SIZE_SHIFT |
 		  4 << URB_STARTING_ADDRESS_SHIFT);
 
-- 
2.0.5