[Intel-gfx] [PATCH] drm/i915/skl: Select DDIA lane capability based upon vbt

Sivakumar Thulasimani sivakumar.thulasimani at intel.com
Thu Apr 23 06:23:06 PDT 2015


we still don't have code to enumerate DDI E or DDI D. but this will 
handle them when this bit is missed by GOP/VBIOS during boot up.

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani at intel.com>


On 4/23/2015 5:58 PM, Sonika Jindal wrote:
> Currently, if bios fails to drive an edp panel due to any reason,
> the ddi buffer will not be enabled. And the DDIA lane capability
> will remain 0. This leads to assumption of DDIA x2 which means DDIA
> supports 2 lanes and DDIE supports 2 lanes. For some higher resolution
> panel which needs 4 lanes, we end up using only 2 lanes which doesn't
> let the modeset go through because of limited data rate avalaible.
>
> So, set the DDIA lane capability correctly if port E is being used
> by any child device or not.
>
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani at intel.com>
> Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h   |    1 +
>   drivers/gpu/drm/i915/intel_bios.c |    4 ++++
>   drivers/gpu/drm/i915/intel_bios.h |    1 +
>   drivers/gpu/drm/i915/intel_ddi.c  |    8 ++++++++
>   4 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 79da7f3..9aad54b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1384,6 +1384,7 @@ struct intel_vbt_data {
>   	union child_device_config *child_dev;
>   
>   	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
> +	unsigned int ddi_e_used;
>   };
>   
>   enum intel_ddb_partitioning {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index c08368c..16c5885 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1119,6 +1119,9 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
>   			dev_priv->vbt.dsi.port = p_child->common.dvo_port;
>   		}
>   
> +		if (p_child->common.dvo_port == DVO_PORT_DPE)
> +			dev_priv->vbt.ddi_e_used = 1;
> +
>   		child_dev_ptr = dev_priv->vbt.child_dev + count;
>   		count++;
>   		memcpy((void *)child_dev_ptr, (void *)p_child,
> @@ -1169,6 +1172,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
>   		info->supports_hdmi = info->supports_dvi;
>   		info->supports_dp = (port != PORT_E);
>   	}
> +	dev_priv->vbt.ddi_e_used = 0;
>   }
>   
>   static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index af0b476..dd85812 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -764,6 +764,7 @@ int intel_parse_bios(struct drm_device *dev);
>   #define DVO_PORT_DPC	8
>   #define DVO_PORT_DPD	9
>   #define DVO_PORT_DPA	10
> +#define DVO_PORT_DPE	11
>   #define DVO_PORT_MIPIA	21
>   #define DVO_PORT_MIPIB	22
>   #define DVO_PORT_MIPIC	23
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b974f8e..c8e370a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2139,6 +2139,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>   	struct intel_encoder *intel_encoder;
>   	struct drm_encoder *encoder;
>   	bool init_hdmi, init_dp;
> +	int val;
>   
>   	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>   		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
> @@ -2169,6 +2170,13 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>   	intel_encoder->get_config = intel_ddi_get_config;
>   
>   	intel_dig_port->port = port;
> +
> +	val = I915_READ(DDI_BUF_CTL(port));
> +	if (IS_SKYLAKE(dev) && port == PORT_A
> +		&& !(val & DDI_BUF_CTL_ENABLE)
> +		&& !dev_priv->vbt.ddi_e_used)
> +		I915_WRITE(DDI_BUF_CTL(port), val | DDI_A_4_LANES);
> +
>   	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
>   					  (DDI_BUF_PORT_REVERSAL |
>   					   DDI_A_4_LANES);

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