[Intel-gfx] [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset

Michel Thierry michel.thierry at intel.com
Wed Aug 5 09:14:33 PDT 2015


On 8/5/2015 4:58 PM, Daniel Vetter wrote:
> On Wed, Jul 29, 2015 at 05:24:01PM +0100, Michel Thierry wrote:
>> There are some allocations that must be only referenced by 32-bit
>> offsets. To limit the chances of having the first 4GB already full,
>> objects not requiring this workaround use DRM_MM_SEARCH_BELOW/
>> DRM_MM_CREATE_TOP flags
>>
>> In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
>> General State Heap (GSH) or Instruction State Heap (ISH) must be in a
>> 32-bit range, because the General State Offset and Instruction State
>> Offset are limited to 32-bits.
>>
>> Objects must have EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag to indicate if
>> they can be allocated above the 32-bit address range. To limit the
>> chances of having the first 4GB already full, objects will use
>> DRM_MM_SEARCH_BELOW + DRM_MM_CREATE_TOP flags when possible.
>>
>> v2: Changed flag logic from neeeds_32b, to supports_48b.
>> v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel)
>> v4: Split pin flags into PIN_ZONE_4G and PIN_HIGH; update PIN_OFFSET_MASK
>> to use last PIN_ defined instead of hard-coded value; use correct limit
>> check in eb_vma_misplaced. (Chris)
>> v5: Don't touch PIN_OFFSET_MASK and update workaround comment (Chris)
>> v6: Apply pin-high for ggtt too (Chris)
>> v7: Handle simultaneous pin-high and pin-mappable end correctly (Akash)
>>      Fix check for entries currently using +4GB addresses, use min_t and
>>      other polish in object_bind_to_vm (Chris)
>>
>> Cc: Chris Wilson <chris at chris-wilson.co.uk>
>> Cc: Akash Goel <akash.goel at intel.com>
>> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> (v4)
>> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
>
> For the record, where can I find the mesa patches for this? I think for
> simple things like this a References: line point to the relevant UMD
> patches in mailing-list archives would be great.
> -Daniel
>

Here they are,

References: 
http://lists.freedesktop.org/archives/dri-devel/2015-July/085501.html 
and http://lists.freedesktop.org/archives/mesa-dev/2015-July/088003.html

The name for the macro will be OUT_RELOC64_INSIDE_4G, as suggested by Chris.



More information about the Intel-gfx mailing list