[Intel-gfx] [SKL-DMC-BUGFIX 3/5] drm/i915/skl: Do not disable cdclk PLL if csr firmware is present.

[Animesh Manna]

On 8/5/2015 2:42 PM, Daniel Vetter wrote:
> On Mon, Aug 03, 2015 at 09:55:34PM +0530, Animesh Manna wrote:
>> While display engine entering into low power state no need to disable
>> cdclk pll as CSR firmware of dmc will take care. If pll is already
>> enabled firmware execution sequence will be blocked. This is one
>> of the criteria for dmc to work properly.
>>
>> Cc: Daniel Vetter <daniel.vetter at intel.com>
>> Cc: Damien Lespiau <damien.lespiau at intel.com>
>> Cc: Imre Deak <imre.deak at intel.com>
>> Cc: Sunil Kamath <sunil.kamath at intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
>> Signed-off-bt: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
>> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj at intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
>>   1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index af0bcfe..ef2ef4d 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5675,10 +5675,13 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>>   	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
>>   		DRM_ERROR("DBuf power disable timeout\n");
>>   
>> -	/* disable DPLL0 */
>> -	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
>> -	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
>> -		DRM_ERROR("Couldn't disable DPLL0\n");
>> +	if (dev_priv->csr.dmc_payload) {
>> +		/* disable DPLL0 */
> Imo this needs a proper comment (and the current one is useless since it
> just states exactly what the code does and is redundant). What about
>
> 	/* DMC assumes ownership of LCPLL and will get confused if we
> 	 * touch it. */
>
> instead before the if?
> -Daniel

Agree, I will add it in my next patch.
(Current comment came from existing code.)

- Animesh

>
>> +		I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
>> +					~LCPLL_PLL_ENABLE);
>> +		if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
>> +			DRM_ERROR("Couldn't disable DPLL0\n");
>> +	}
>>   
>>   	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>>   }
>> -- 
>> 2.0.2
>>
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