[Intel-gfx] [PATCH] drm/i915: clflush on pin_to_display after pwrite to UC bo in LLC

[Chris Wilson]

On Tue, Aug 11, 2015 at 06:10:29PM +0300, Ville Syrjälä wrote:
> On Tue, Aug 11, 2015 at 05:56:28PM +0300, Ville Syrjälä wrote:
> > Hmm. So what would happen on !LLC if we start with a cached bo, then pwrite it
> > and afterwards make it uncached?
> 
> In fact that would still fail even with my patch, and wouldn't work with current
> upstream code either. To fix that I'd need to drop the I915_CACHE_NONE/WT checks
> from pwrite in my patch and always set cache_dirty=true when it didn't
> clflush. Doing that would seem perfectly reasonable to me.

Yes. I agree. Marking obj->cache_dirty whenever we dirty the cpu cache
and clear it upon clflush seems sane. It will only take effect on
transition to the display plane, so not going to impact us except when
correctness is required. So maybe we should call it obj->display_dirty?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre