[Intel-gfx] [PATCH v2 2/2] drm/i915/bxt: work around HW coherency issue for cached GEM mappings

[Chris Wilson]

On Fri, Aug 14, 2015 at 03:38:57PM +0300, Imre Deak wrote:
> Due to a coherency issue on BXT A steppings we can't guarantee a
> coherent view of cached GPU mappings, so fall back to uncached mappings.
> Note that this still won't fix cases where userspace expects a coherent
> view without synchronizing (via a set domain call). It still makes sense
> to limit the kernel's notion of the mapping to be uncached, for example
> for relocations to work properly during execbuffer time. Also in case
> user space does synchronize the buffer, this will still guarantee that
> we'll do the proper clflushing for the buffer.
> 
> v2:
> - limit the WA to A steppings, on later stepping this HW issue is fixed

This has to report the failure, ENODEV otherwise userspace will be
terribly confused (it will try to CPU coherent access assuming it will
be fast, when it is better to use alternative paths).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre