[Intel-gfx] [PATCH] drm/i915: Mark the GTT as uncached, not WC, for Cherryview

[Chris Wilson]

I traced a stability issue on my Braswell nuc to a lack of visibility of
PTE writes into the GTT by the GPU. (The smoking gun was GPU hangs with
random fault addresses but correct command streams). Adding clflushes or
kicking the chipset flush harder had no effect, only disabling the WC
cache for the GSM like for Broxton removed the hangs.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: stable at vger.kernel.org
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 10efdc11c2e6..1f685e630d73 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2791,8 +2791,10 @@ static int ggtt_probe_common(struct drm_device *dev,
 	 * when the WC buffer is flushed, so we can't use it, but have to
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
+	 *
+	 * Hmm, it seems that BSW also has a similar deficiency...
 	 */
-	if (IS_BROXTON(dev))
+	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
 		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
 	else
 		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
-- 
2.5.0