[Intel-gfx] [PATCH v2] drm/i915: Change SRM, LRM instructions to use correct length

[Mika Kuoppala]

Arun Siluvery <arun.siluvery at linux.intel.com> writes:

> MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM instructions are not really
> variable length instructions unlike MI_LOAD_REGISTER_IMM where it expects
> (reg, addr) pairs so use fixed length for these instructions.
>
> v2: rebase
>
> Cc: Dave Gordon <david.s.gordon at intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h        | 8 ++++----
>  drivers/gpu/drm/i915/intel_display.c   | 4 ++--
>  drivers/gpu/drm/i915/intel_lrc.c       | 4 ++--
>  4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 430571b..3771922 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
>  	CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
>  	CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
>  	      .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
> -	CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,
> +	CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  1,     W | B,
>  	      .reg = { .offset = 1, .mask = 0x007FFFFC },
>  	      .bits = {{
>  			.offset = 0,
>  			.mask = MI_GLOBAL_GTT,
>  			.expected = 0,
>  	      }},						       ),
> -	CMD(  MI_LOAD_REGISTER_MEM(1),             SMI,   !F,  0xFF,   W | B,
> +	CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  1,     W | B,
>  	      .reg = { .offset = 1, .mask = 0x007FFFFC },
>  	      .bits = {{
>  			.offset = 0,
> @@ -1021,7 +1021,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
>  			 * only MI_LOAD_REGISTER_IMM commands.
>  			 */
>  			if (reg_addr == OACONTROL) {
> -				if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {
> +				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
>  					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
>  					return false;
>  				}
> @@ -1035,7 +1035,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
>  			 * allowed mask/value pair given in the whitelist entry.
>  			 */
>  			if (reg->mask) {
> -				if (desc->cmd.value == MI_LOAD_REGISTER_MEM(1)) {
> +				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
>  					DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
>  							 reg_addr);
>  					return false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 827714c..e1a8876 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -343,8 +343,8 @@
>   */
>  #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
>  #define   MI_LRI_FORCE_POSTED		(1<<12)
> -#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
> -#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
> +#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
> +#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
>  #define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
>  #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
>  #define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
> @@ -355,8 +355,8 @@
>  #define   MI_INVALIDATE_BSD		(1<<7)
>  #define   MI_FLUSH_DW_USE_GTT		(1<<2)
>  #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
> -#define MI_LOAD_REGISTER_MEM(x) MI_INSTR(0x29, 2*(x)-1)
> -#define MI_LOAD_REGISTER_MEM_GEN8(x) MI_INSTR(0x29, 3*(x)-1)
> +#define MI_LOAD_REGISTER_MEM 	   MI_INSTR(0x29, 1)
> +#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)

Minor nitpick: checkpatch complained about there being space before
tab in here.

Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

>  #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
>  #define   MI_BATCH_NON_SECURE		(1)
>  /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index af0bcfe..e8f1c95 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11123,10 +11123,10 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
>  					DERRMR_PIPEB_PRI_FLIP_DONE |
>  					DERRMR_PIPEC_PRI_FLIP_DONE));
>  		if (IS_GEN8(dev))
> -			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
> +			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
>  					      MI_SRM_LRM_GLOBAL_GTT);
>  		else
> -			intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
> +			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
>  					      MI_SRM_LRM_GLOBAL_GTT);
>  		intel_ring_emit(ring, DERRMR);
>  		intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index d3a03f3..99a7820 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1106,7 +1106,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
>  	if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0)
>  		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
>  
> -	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) |
> +	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
>  				   MI_SRM_LRM_GLOBAL_GTT));
>  	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
>  	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
> @@ -1124,7 +1124,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
>  	wa_ctx_emit(batch, index, 0);
>  	wa_ctx_emit(batch, index, 0);
>  
> -	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) |
> +	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
>  				   MI_SRM_LRM_GLOBAL_GTT));
>  	wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
>  	wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
> -- 
> 1.9.1