[Intel-gfx] [PATCH 13/13] drm/i915/skl: Clarify pending vs hw watermark values

[Matt Roper]

Although we calculate watermark values in the atomic state, we still
have both 'pending' and 'hardware' values that ultimately wind up in
dev_priv due to the somewhat complicated watermark flushing process.
Re-arranging how these are stored/named in the dev_priv substructure may
add a little bit of clarity to what they're for.

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h      | 29 +++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_display.c |  4 ++--
 drivers/gpu/drm/i915/intel_pm.c      | 12 ++++++------
 4 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 54508f1..2a24141 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3134,7 +3134,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 
 	drm_modeset_lock_all(dev);
 
-	ddb = &dev_priv->wm.skl_hw.ddb;
+	ddb = &dev_priv->wm.skl.hw.ddb;
 
 	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be42dd8..c4ba9a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1918,17 +1918,30 @@ struct drm_i915_private {
 		/* Committed wm config */
 		struct intel_wm_config config;
 
-		/*
-		 * The skl_wm_values structure is a bit too big for stack
-		 * allocation, so we keep the staging struct where we store
-		 * intermediate results here instead.
-		 */
-		struct skl_wm_values skl_results;
-
 		/* current hardware state */
 		union {
 			struct ilk_wm_values hw;
-			struct skl_wm_values skl_hw;
+			struct {
+				/*
+				 * The skl_wm_values structure is a bit too big
+				 * for stack allocation, so we keep the staging
+				 * struct where we store intermediate results
+				 * here instead.
+				 *
+				 * These watermark values correspond to the
+				 * state that has been swapped into the various
+				 * DRM objects, but may not have been
+				 * completely written to hardware yet due to
+				 * the multi-step flushing process.
+				 */
+				struct skl_wm_values pending;
+
+				/*
+				 * Watermark values that have been fully
+				 * written and flushed to the hardware.
+				 */
+				struct skl_wm_values hw;
+			} skl;
 			struct vlv_wm_values vlv;
 		};
 	} wm;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0a0e7f7..c58a83b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12581,7 +12581,7 @@ static void check_wm_state(struct drm_device *dev)
 		return;
 
 	skl_ddb_get_hw_state(dev_priv, &hw_ddb);
-	sw_ddb = &dev_priv->wm.skl_hw.ddb;
+	sw_ddb = &dev_priv->wm.skl.hw.ddb;
 
 	for_each_intel_crtc(dev, intel_crtc) {
 		struct skl_ddb_entry *hw_entry, *sw_entry;
@@ -13192,7 +13192,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 	drm_atomic_helper_swap_state(dev, state);
 	dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
-	dev_priv->wm.skl_results = to_intel_atomic_state(state)->skl_wm;
+	dev_priv->wm.skl.pending = to_intel_atomic_state(state)->skl_wm;
 
 	for_each_crtc_in_state(state, crtc, crtc_state, i) {
 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a9e9e57..f1c989c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3183,7 +3183,7 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
+	const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl.hw.ddb;
 	enum pipe pipe = intel_crtc->pipe;
 
 	if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
@@ -3529,7 +3529,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 
 	new_ddb = &new_values->ddb;
-	cur_ddb = &dev_priv->wm.skl_hw.ddb;
+	cur_ddb = &dev_priv->wm.skl.hw.ddb;
 
 	/*
 	 * First pass: flush the pipes with the new allocation contained into
@@ -3693,13 +3693,13 @@ static int skl_compute_wm(struct drm_crtc *crtc,
 
 static void skl_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct skl_wm_values *results = &dev_priv->wm.skl_results;
+	struct skl_wm_values *results = &dev_priv->wm.skl.pending;
 
 	skl_write_wm_values(dev_priv, results);
 	skl_flush_wm_values(dev_priv, results);
 
 	/* store the new configuration */
-	dev_priv->wm.skl_hw = *results;
+	dev_priv->wm.skl.hw = *results;
 }
 
 
@@ -3790,7 +3790,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+	struct skl_wm_values *hw = &dev_priv->wm.skl.hw;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
 	struct skl_pipe_wm *active = &cstate->wm.skl;
@@ -3842,7 +3842,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
+	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl.hw.ddb;
 	struct drm_crtc *crtc;
 
 	skl_ddb_get_hw_state(dev_priv, ddb);
-- 
2.1.4