[Intel-gfx] [PATCH 3/3] drm/i915: Only move to the CPU write domain if keeping the GTT pages

[Chris Wilson]

On Mon, Aug 24, 2015 at 05:28:16PM +0530, ankitprasad.r.sharma at intel.com wrote:
> +		/*
> +		 * the cached mapping could lead to stale cachelines, so an
> +		 * invalidation is needed for the object pages, when they are
> +		 * released back to kernel
> +		 */

Multiline comments should be full sentences (i.e. captilised and punctuated).

> +		(to_intel_bo(obj))->has_stale_cachelines = 1;

Was there a buy one, get one free other on brackets? Is there a bug in
the to_intel_bo() macro?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre