[Intel-gfx] [PATCH 12/15] drm/i915: Force CL2 off in CHV x1 PHY

[Daniel Vetter]

On Wed, Aug 19, 2015 at 04:39:41PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 19, 2015 at 06:52:57PM +0530, Deepak wrote:
> > 
> > 
> > On 07/09/2015 02:15 AM, ville.syrjala at linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > >
> > > We can choose to leave the display PHY CL2 powerdown up to some hardware
> > > signals, or we can force it. The BXT code forces the nonexistent CL2 in
> > > the x1 PHY to power down. Follow suit on CHV. Maybe it can still save
> > > some extra power by disabling some extra logic in CL1, or something.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/i915_reg.h         | 1 +
> > >   drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++++++++
> > >   2 files changed, 10 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8010200..395f556 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1139,6 +1139,7 @@ enum skl_disp_power_wells {
> > >   #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
> > >   
> > >   #define CHV_CMN_DW30			0x8178
> > > +#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
> > >   #define   DPIO_LRC_BYPASS		(1 << 3)
> > >   
> > >   #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 37e4375..002b78f 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -980,6 +980,15 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> > >   		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
> > >   		tmp |= DPIO_DYNPWRDOWNEN_CH1;
> > >   		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
> > > +	} else {
> > > +		/*
> > > +		 * Force the non-existing CL2 off. BXT does this
> > > +		 * too, so maybe it saves some power even though
> > > +		 * CL2 doesn't exist?
> > > +		 */
> > > +		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> > > +		tmp |= DPIO_CL2_LDOFUSE_PWRENB;
> > > +		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
> > >   	}
> > >   
> > Do we need to turn off CL2 each time we enable dpio cmn power wells?
> 
> Yes, all DPIO registers lose their state when the power well is off.
> 
> > 
> > btw, changes looks fine
> > Reviewed-by: Deepak S <deepak.s at linux.intel.com>

Merged up to this one with the one patch from the dpll series
cherry-picked. Later patches seem to still lack r-bs.

Thanks, Daniel
> > 
> > 
> > >   	mutex_unlock(&dev_priv->sb_lock);
> > 
> > _______________________________________________
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> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch