[Intel-gfx] [PATCH] drm/i915/guc: Support GuC version 4.3

[Dave Gordon]

On 18/08/15 22:32, yu.dai at intel.com wrote:
> From: Alex Dai <yu.dai at intel.com>
>
> The firmware layout changes that now it only has css header +
> uCode + RSA signature. Plus, other trivial changes to support
> GuC V4.3.
>
> Signed-off-by: Alex Dai <yu.dai at intel.com>

Reviewed-by: Dave Gordon <david.s.gordon at intel.com>

This works with the version 4.3 binary currently available for download 
from 01.org :)

> ---
>   drivers/gpu/drm/i915/intel_guc_fwif.h   | 11 ++++++++---
>   drivers/gpu/drm/i915/intel_guc_loader.c | 17 ++++++-----------
>   2 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 950c7e7..e1f47ba 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -41,7 +41,7 @@
>   #define GUC_CTX_PRIORITY_NORMAL		3
>
>   #define GUC_MAX_GPU_CONTEXTS		1024
> -#define	GUC_INVALID_CTX_ID		(GUC_MAX_GPU_CONTEXTS + 1)
> +#define	GUC_INVALID_CTX_ID		GUC_MAX_GPU_CONTEXTS
>
>   /* Work queue item header definitions */
>   #define WQ_STATUS_ACTIVE		1
> @@ -75,6 +75,7 @@
>   #define GUC_CTX_DESC_ATTR_RESET		(1 << 4)
>   #define GUC_CTX_DESC_ATTR_WQLOCKED	(1 << 5)
>   #define GUC_CTX_DESC_ATTR_PCH		(1 << 6)
> +#define GUC_CTX_DESC_ATTR_TERMINATED	(1 << 7)
>
>   /* The guc control data is 10 DWORDs */
>   #define GUC_CTL_CTXINFO			0
> @@ -107,6 +108,7 @@
>   #define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
>   #define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
>   #define   GUC_CTL_ENABLE_SLPC		(1 << 7)
> +#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)
>   #define GUC_CTL_DEBUG			8
>   #define   GUC_LOG_VERBOSITY_SHIFT	0
>   #define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
> @@ -116,8 +118,9 @@
>   /* Verbosity range-check limits, without the shift */
>   #define	  GUC_LOG_VERBOSITY_MIN		0
>   #define	  GUC_LOG_VERBOSITY_MAX		3
> +#define GUC_CTL_RSRVD			9
>
> -#define GUC_CTL_MAX_DWORDS		(GUC_CTL_DEBUG + 1)
> +#define GUC_CTL_MAX_DWORDS		(GUC_CTL_RSRVD + 1)
>
>   struct guc_doorbell_info {
>   	u32 db_status;
> @@ -207,7 +210,9 @@ struct guc_context_desc {
>
>   	u32 engine_presence;
>
> -	u32 reserved0[1];
> +	u8 engine_suspended;
> +
> +	u8 reserved0[3];
>   	u64 reserved1[1];
>
>   	u64 desc_private;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index d46195c..7521eac 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -59,7 +59,7 @@
>    *
>    */
>
> -#define I915_SKL_GUC_UCODE "i915/skl_guc_ver3.bin"
> +#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
>   MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
>
>   /* User-friendly representation of an enum */
> @@ -226,10 +226,6 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
>    * +-------------------------------+  ----
>    * |         RSA signature         |  256B
>    * +-------------------------------+  ----
> - * |         RSA public Key        |  256B
> - * +-------------------------------+  ----
> - * |       Public key modulus      |    4B
> - * +-------------------------------+  ----
>    *
>    * Architecturally, the DMA engine is bidirectional, and can potentially even
>    * transfer between GTT locations. This functionality is left out of the API
> @@ -244,7 +240,6 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
>   #define UOS_VER_MAJOR_OFFSET		0x46
>   #define UOS_CSS_HEADER_SIZE		0x80
>   #define UOS_RSA_SIG_SIZE		0x100
> -#define UOS_CSS_SIGNING_SIZE		0x204
>
>   static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>   {
> @@ -256,7 +251,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
>   	int i, ret = 0;
>
>   	/* uCode size, also is where RSA signature starts */
> -	offset = ucode_size = guc_fw->guc_fw_size - UOS_CSS_SIGNING_SIZE;
> +	offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
>   	I915_WRITE(DMA_COPY_SIZE, ucode_size);
>
>   	/* Copy RSA signature from the fw image to HW for verification */
> @@ -471,8 +466,8 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
>   	struct drm_i915_gem_object *obj;
>   	const struct firmware *fw;
>   	const u8 *css_header;
> -	const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_CSS_SIGNING_SIZE;
> -	const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_CSS_SIGNING_SIZE
> +	const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
> +	const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
>   			- 0x8000; /* 32k reserved (8K stack + 24k context) */
>   	int err;
>
> @@ -572,8 +567,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
>   		fw_path = NULL;
>   	} else if (IS_SKYLAKE(dev)) {
>   		fw_path = I915_SKL_GUC_UCODE;
> -		guc_fw->guc_fw_major_wanted = 3;
> -		guc_fw->guc_fw_minor_wanted = 0;
> +		guc_fw->guc_fw_major_wanted = 4;
> +		guc_fw->guc_fw_minor_wanted = 3;
>   	} else {
>   		i915.enable_guc_submission = false;
>   		fw_path = "";	/* unknown device */
>