[Intel-gfx] [PATCH] drm/i915: Wait for PP cycle delay only if panel is in power off sequence

[Ville Syrjälä]

On Wed, Dec 09, 2015 at 06:51:48PM +0530, Shobhit Kumar wrote:
> During resume, while turning the EDP panel power on, we need not wait
> blindly for panel_power_cycle_delay. Check if panel power down sequence
> in progress and then only wait. This improves our resume time significantly.
> 
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f335c92..10ec669 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -617,6 +617,20 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>  	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
>  }
>  
> +static bool edp_panel_off_seq(struct intel_dp *intel_dp)
> +{
> +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	lockdep_assert_held(&dev_priv->pps_mutex);
> +
> +	if (IS_VALLEYVIEW(dev) &&
> +	    intel_dp->pps_pipe == INVALID_PIPE)
> +		return false;
> +
> +	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_SEQUENCE_POWER_DOWN) != 0;
> +}

This doens't make sense to me. The power down cycle may have
completed just before, and so this would claim we don't have to
wait for the power_cycle_delay.

> +
>  static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>  {
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> @@ -2025,7 +2039,8 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>  		 port_name(dp_to_dig_port(intel_dp)->port)))
>  		return;
>  
> -	wait_panel_power_cycle(intel_dp);
> +	if (edp_panel_off_seq(intel_dp))
> +		wait_panel_power_cycle(intel_dp);
>  
>  	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
>  	pp = ironlake_get_pp_control(intel_dp);
> -- 
> 2.4.3

-- 
Ville Syrjälä
Intel OTC