[Intel-gfx] [PATCH 2/9] drm/i915: Use insert_page for pwrite_fast

Chris Wilson chris at chris-wilson.co.uk
Mon Dec 14 01:54:06 PST 2015


On Mon, Dec 14, 2015 at 11:16:04AM +0530, ankitprasad.r.sharma at intel.com wrote:
> From: Ankitprasad Sharma <ankitprasad.r.sharma at intel.com>
> 
> In pwrite_fast, map an object page by page if obj_ggtt_pin fails. First,
> we try a nonblocking pin for the whole object (since that is fastest if
> reused), then failing that we try to grab one page in the mappable
> aperture. It also allows us to handle objects larger than the mappable
> aperture (e.g. if we need to pwrite with vGPU restricting the aperture
> to a measely 8MiB or something like that).
> 
> v2: Pin pages before starting pwrite, Combined duplicate loops (Chris)
> 
> v3: Combined loops based on local patch by Chris (Chris)
> 
> v4: Added i915 wrapper function for drm_mm_insert_node_in_range (Chris)
> 
> Signed-off-by: Ankitprasad Sharma <ankitprasad.r.sharma at intel.com>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 86 ++++++++++++++++++++++++++++++-----------
>  1 file changed, 64 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index bf7f203..46c1e75 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -61,6 +61,21 @@ static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
>  	return obj->pin_display;
>  }
>  
> +static int
> +i915_gem_insert_node_in_range(struct drm_i915_private *i915,
> +			      struct drm_mm_node *node, u64 size,
> +			      unsigned alignment, u64 start, u64 end)
> +{
> +	int ret;
> +
> +	ret = drm_mm_insert_node_in_range_generic(&i915->gtt.base.mm, node,
> +						  size, alignment, 0, start,
> +						  end, DRM_MM_SEARCH_DEFAULT,
> +						  DRM_MM_SEARCH_DEFAULT);
> +
> +	return ret;
> +}

No. It encodes a very bad assumption (i915->gtt) that is not made clear
in anyway.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre


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