[Intel-gfx] [PATCH 07/18] drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Nick Hoath]

On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath at intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578fd90..cb66c8f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5237,12 +5237,16 @@ enum skl_disp_power_wells {
>   /* GEN7 chicken */
>   #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
>   # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
> +# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
>   #define COMMON_SLICE_CHICKEN2			0x7014
>   # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
>
>   #define HIZ_CHICKEN				0x7018
>   # define CHV_HZ_8X8_MODE_IN_1X			(1<<15)
>
> +#define GEN9_SLICE_COMMON_ECO_CHICKEN0		0x7308
> +#define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> +
>   #define GEN7_L3SQCREG1				0xB010
>   #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 293d1b6..b15d596 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -897,6 +897,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   			~GEN9_DG_MIRROR_FIX_ENABLE);
>   	}
>
> +	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
> +		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
> +		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> +				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> +		WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
> +				  DISABLE_PIXEL_MASK_CAMMING);
> +	}
> +
>   	if (INTEL_REVID(dev) >= SKL_REVID_C0) {
>   		/* WaEnableYV12BugFixInHalfSliceChicken7:skl */
>   		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>