[Intel-gfx] [PATCH 0/3] Restore pipe interrupts registers after power well enabling

[Damien Lespiau]

Just like BDW, those registers are on the respective pipe powell, and if we
don't restore them bad things happen! like not flipping anymore because the
primary plane flip done interrupt is disabled.

With that, the torture test that is kms_flip seems to be fairly happy, it's
been running (and passing tests) for a good 20 minutes and is still going.

-- 
Damien

Damien Lespiau (3):
  drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
  drm/i915/skl: Restore pipe interrupt registers after power well
    enabling
  drm/i915: Remove unused condition in hsw_power_well_post_enable()

 drivers/gpu/drm/i915/i915_irq.c         | 19 ++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h        |  3 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 36 +++++++++++++++++++++++++++++++--
 3 files changed, 50 insertions(+), 8 deletions(-)

-- 
1.8.3.1