[Intel-gfx] [PATCH 2/3] drm/i915: gen 9 h/w w/a (WaDisablePooledEuLoadBalancingFix)

[Damien Lespiau]

On Wed, Feb 18, 2015 at 03:16:07PM +0000, Nick Hoath wrote:
> Signed-off-by: Nick Hoath <nicholas.hoath at intel.com>
> ---

This one isn't listed for SKL.

-- 
Damien

>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39bdbf9..7f9150b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1462,6 +1462,9 @@ enum skl_disp_power_wells {
>  #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
>  #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
>  
> +#define GEN9_FF_SLICE_CS_CHICKEN2				0x020e4
> +#define   GEN9_CHICKEN_BIT_POOLED_EU_LOAD_BALANCE_FIX_DISABLE	(1<<10)
> +
>  #define CACHE_MODE_0	0x02120 /* 915+ only */
>  #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
>  #define   CM0_IZ_OPT_DISABLE      (1<<6)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f67e491..4fe71db5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -81,6 +81,15 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  		/* WaDisableLSQCROPERFforOCL:skl */
>  		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
>  			   GEN8_LQSC_RO_PERF_DIS);
> +
> +	if (INTEL_REVID(dev) == SKL_REVID_A0) {
> +		/*
> +		 * WaDisablePooledEuLoadBalancingFix:skl
> +		 */
> +		I915_WRITE(GEN9_FF_SLICE_CS_CHICKEN2,
> +			_MASKED_BIT_ENABLE(
> +			GEN9_CHICKEN_BIT_POOLED_EU_LOAD_BALANCE_FIX_DISABLE));
> +	}
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.1.1
> 
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