[Intel-gfx] [PATCH] drm/i915/hsw: enable atomic in L3 for some steppings.

[shuang.he at intel.com]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  363/364              363/364
ILK                                  364/366              364/366
SNB              +2                 443/450              445/450
IVB                                  496/498              496/498
BYT                                  288/289              288/289
HSW              +3-1              542/564              544/564
BDW                                  415/417              415/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(3, M35)      PASS(1, M35)
 SNB  igt_kms_plane_plane-position-hole-pipe-B-plane-1      DMESG_WARN(1, M35)PASS(3, M35M22)      PASS(1, M35)
*HSW  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M40)      PASS(1, M40)
 HSW  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset      DMESG_WARN(1, M40)PASS(3, M40M19)      DMESG_WARN(1, M40)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1      TIMEOUT(2, M40)PASS(2, M19M40)      PASS(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M19)DMESG_WARN(1, M40)PASS(2, M40)      PASS(1, M40)
Note: You need to pay more attention to line start with '*'