[Intel-gfx] [PATCH] drm/i915: Make sample_c messages go faster on Haswell.

[Daniel Vetter]

On Wed, Dec 31, 2014 at 04:23:00PM -0800, Kenneth Graunke wrote:
> Haswell significantly improved the performance of sampler_c messages,
> but the optimization appears to be off by default.  Later platforms
> remove this bit, and apparently always enable the optimization.
> 
> Improves performance in "Counter Strike: Global Offensive" by 18%
> at default settings on Iris Pro.
> 
> This may break sampling of paletted formats (P8/A8P8/P8A8).  It's
> unclear whether it affects sampling of paletted formats in general,
> or just the sample_c message (which is never used).
> 
> While libva does have support for using paletted formats (primarily
> for OSDs), that support appears to have been broken for at least a
> year, so I couldn't observe a regression from this.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> Resubmitting the patch to unconditionally enable this.  I tried to get
> libva-intel to use paletted formats, and observe a regression...but the
> only thing I found that used it was mplayer's OSD (on screen display).
> Even without my patch, the colors were totally wrong with that, and it's
> according to a few distro wikis, that's been the case for over a year.
> 
> If libva's code for paletted formats /is/ broken, they could always add
> code to disable this bit using the command validator when fixing it.
> 
> Could we try merging this, and back it out if someone reports a
> regression?  I haven't observed any problems.  It's also been quite
> stable.

Yeah makes sense. When resending please incorporated review feedback
(Ville dug out the wa name), I've done that. And I've pasted the
additional detail about the libva saga, just for reference (since no one
will remember that it's mplayer's OSD which uses this 2 months down the
road).

Also please cc libva mailing lists next time around as an fyi. Done that
too.

Queued for -next, thanks for the patch.
-Daniel

> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 40ca873..0f32fd1a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6167,6 +6167,7 @@ enum punit_power_well {
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>  
>  #define HALF_SLICE_CHICKEN3		0xe184
> +#define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7d99a9c..17e84dc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5974,6 +5974,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_GT_MODE,
>  		   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
>  
> +	/* Make sample_c messages faster. */
> +	I915_WRITE(HALF_SLICE_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
> +
>  	/* WaSwitchSolVfFArbitrationPriority:hsw */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  
> -- 
> 2.2.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch