[Intel-gfx] [PATCH] drm/i915: Enable the HiZ RAW Stall Optimization on Gen8.

[Kenneth Graunke]

On Monday, January 12, 2015 02:32:20 PM Ville Syrjälä wrote:
> On Sat, Jan 10, 2015 at 06:44:49PM -0800, Kenneth Graunke wrote:
> > This is an important optimization for avoiding read-after-write (RAW)
> > stalls in the HiZ buffer.  Certain workloads would run very slowly with
> > HiZ enabled, but run much faster with the "hiz=false" driconf option.
> > With this patch, they run at full speed even with HiZ.
> > 
> > Improves performance in OglVSInstancing by 3.2x on Broadwell GT3e
> > (Iris Pro 6200).
> > 
> > Thanks to Jesse Barnes for finding this missing bit!
> > Thanks to Chris Wilson for helping me find where to set it.
> > 
> > Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> > Cc: Jesse Barnes <jbarnes at virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > Here's an alternate patch which implements the workaround in the kernel
> > instead of Mesa.  It's probably better to do it there, since the kernel
> > does it on Haswell already.
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index dabc1d8..23020d6 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -796,6 +796,16 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> >  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> >  			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
> >  
> > +	/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> > +	 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
> > +	 *  polygons in the same 8x4 pixel/sample area to be processed without
> > +	 *  stalling waiting for the earlier ones to write to Hierarchical Z
> > +	 *  buffer."
> > +	 *
> > +	 * This optimization is off by default for Broadwell; turn it on.
> > +	 */
> > +	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> > +
> >  	/* Wa4x4STCOptimizationDisable:bdw */
> >  	WA_SET_BIT_MASKED(CACHE_MODE_1,
> >  			  GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> > @@ -836,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> >  			  HDC_FORCE_NON_COHERENT |
> >  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
> >  
> > +	/* According to the CACHE_MODE_0 default value documentation, some
> > +	 * CHV platforms disable this optimization by default.  Turn it on.
> > +	 */
> > +	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
> > +
> 
> I remember looking at this when the HSW version was done, and at the
> time the docs claimed that the default value on gen8 was already good.
> Looks like the docs have been updated since then. Also my BSW agrees
> that the disable bit is now set by default.
> 
> I suppose we could assume that since it works on HSW, it'll work on
> gen8. However, I find it a bit suspicious that the later steppings seem
> to have changed the default to disable the optimization. IVB suffered
> from real problems with the optimization enabled and hence the IVB patch
> was reverted. IIRC Chia-I wrote some kind of test to demonstrate the
> problem on IVB, so maybe you want to run it and make sure it still
> works correctly on gen8. Here's the test:
> http://permalink.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/35399

I just ran Chia-I's program on BSW, and it appears to be working fine.
Classic swrast and i965/hardware both produced an identical image.

--Ken
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