[Intel-gfx] [PATCH v3 18/25] drm/i915/bdw: pagetable allocation rework
Michel Thierry
michel.thierry at intel.com
Tue Jan 13 03:52:32 PST 2015
From: Ben Widawsky <benjamin.widawsky at intel.com>
Start using gen8_for_each_pde macro to allocate page tables.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Signed-off-by: Michel Thierry <michel.thierry at intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 ++++++++++++++++++++-----------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++++++
2 files changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3779653..1a070b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -602,14 +602,6 @@ static void gen8_teardown_va_range(struct i915_address_space *vm,
}
}
-/* This function will die soon */
-static void gen8_free_full_page_directory(struct i915_hw_ppgtt *ppgtt, int i)
-{
- gen8_teardown_va_range(&ppgtt->base,
- i << GEN8_PDPE_SHIFT,
- (1 << GEN8_PDPE_SHIFT));
-}
-
static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
{
struct pci_dev *hwdev = ppgtt->base.dev->pdev;
@@ -653,22 +645,27 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
gen8_ppgtt_free(ppgtt);
}
-static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
+static int gen8_ppgtt_alloc_pagetabs(struct i915_page_directory_entry *pd,
+ uint64_t start,
+ uint64_t length,
+ struct drm_device *dev)
{
- int i, ret;
+ struct i915_page_table_entry *unused;
+ uint64_t temp;
+ uint32_t pde;
- for (i = 0; i < ppgtt->num_pd_pages; i++) {
- ret = alloc_pt_range(ppgtt->pdp.page_directory[i],
- 0, GEN8_PDES_PER_PAGE, ppgtt->base.dev);
- if (ret)
+ gen8_for_each_pde(unused, pd, start, length, temp, pde) {
+ BUG_ON(unused);
+ pd->page_tables[pde] = alloc_pt_single(dev);
+ if (IS_ERR(pd->page_tables[pde]))
goto unwind_out;
}
return 0;
unwind_out:
- while (i--)
- gen8_free_full_page_directory(ppgtt, i);
+ while (pde--)
+ unmap_and_free_pt(pd->page_tables[pde], dev);
return -ENOMEM;
}
@@ -711,20 +708,28 @@ unwind_out:
}
static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
- const int max_pdp)
+ uint64_t start,
+ uint64_t length)
{
+ struct i915_page_directory_entry *pd;
+ uint64_t temp;
+ uint32_t pdpe;
int ret;
- ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, ppgtt->base.start,
- ppgtt->base.total);
+ ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, start, length);
if (ret)
return ret;
- ret = gen8_ppgtt_allocate_page_tables(ppgtt);
- if (ret)
- goto err_out;
+ gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
+ ret = gen8_ppgtt_alloc_pagetabs(pd, start, length,
+ ppgtt->base.dev);
+ if (ret)
+ goto err_out;
+
+ ppgtt->num_pd_entries += GEN8_PDES_PER_PAGE;
+ }
- ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
+ BUG_ON(pdpe > ppgtt->num_pd_pages);
return 0;
@@ -795,10 +800,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
ppgtt->base.start = 0;
ppgtt->base.total = size;
- BUG_ON(ppgtt->base.total == 0);
/* 1. Do all our allocations for page directories and page tables. */
- ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
+ ret = gen8_ppgtt_alloc(ppgtt, ppgtt->base.start, ppgtt->base.total);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c82a029..f416e01 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -401,6 +401,16 @@ static inline uint32_t gen6_pde_index(uint32_t addr)
temp = min(temp, length), \
start += temp, length -= temp)
+/* Clamp length to the next pagetab boundary */
+static inline uint64_t gen8_clamp_pt(uint64_t start, uint64_t length)
+{
+ uint64_t next_pt = ALIGN(start + 1, 1 << GEN8_PDE_SHIFT);
+ if (next_pt > (start + length))
+ return length;
+
+ return next_pt - start;
+}
+
/* Clamp length to the next page_directory boundary */
static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length)
{
--
2.1.1
More information about the Intel-gfx
mailing list