[Intel-gfx] [PATCH v2 3/3] drm/i915: Ensure the HiZ RAW Stall Optimization is on for Cherryview.

Kenneth Graunke kenneth at whitecape.org
Tue Jan 13 12:46:53 PST 2015

This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer.  Certain workloads would run very slowly with
HiZ enabled, but run much faster with the "hiz=false" driconf option.
With this patch, they run at full speed even with HiZ.

Increases performance in OglVSInstancing by about 2.7x on Braswell.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
 1 file changed, 5 insertions(+)

Split, as requested by Ben.

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0df15a4..23020d6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
+	/* According to the CACHE_MODE_0 default value documentation, some
+	 * CHV platforms disable this optimization by default.  Turn it on.
+	 */
 	/* Improve HiZ throughput on CHV. */

More information about the Intel-gfx mailing list