[Intel-gfx] [PATCH 7/9] drm/i915: PSR VLV/CHV: let's respect link_standby here as well.

[Rodrigo Vivi]

Sure, please ignore this patch for now...

Also this one was a wrong version without a needed parenthesis on
transmitter line, so it was actually disabling PSR on CHV.

On Tue, Jan 13, 2015 at 6:46 AM, R, Durgadoss <durgadoss.r at intel.com> wrote:
>>-----Original Message-----
>>From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of Rodrigo Vivi
>>Sent: Monday, January 12, 2015 11:45 PM
>>To: intel-gfx at lists.freedesktop.org
>>Cc: Vivi, Rodrigo
>>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: PSR VLV/CHV: let's respect link_standby here as well.
>>
>>Let's respect vbt and panel for link_standby/on x link_disabled
>>
>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>>---
>> drivers/gpu/drm/i915/intel_psr.c | 16 +++++++++++++---
>> 1 file changed, 13 insertions(+), 3 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>index 5ae193e..313347a 100644
>>--- a/drivers/gpu/drm/i915/intel_psr.c
>>+++ b/drivers/gpu/drm/i915/intel_psr.c
>>@@ -132,8 +132,17 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
>>
>> static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>> {
>>-      drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>-                         DP_PSR_ENABLE);
>>+      struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>+      struct drm_device *dev = dig_port->base.base.dev;
>>+      struct drm_i915_private *dev_priv = dev->dev_private;
>>+
>>+      /* Enable PSR in sink */
>>+      if (dev_priv->psr.link_standby)
>>+              drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>+                                 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>>+      else
>>+              drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>+                                 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
>> }
>>
>> static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>>@@ -183,11 +192,12 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp)
>>       struct drm_i915_private *dev_priv = dev->dev_private;
>>       struct drm_crtc *crtc = dig_port->base.base.crtc;
>>       enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>+      bool standby = dev_priv->psr.link_standby;
>>
>>       /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
>>       I915_WRITE(VLV_PSRCTL(pipe),
>>                  VLV_EDP_PSR_MODE_SW_TIMER |
>>-                 VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
>>+                 standby ? VLV_EDP_PSR_SRC_TRANSMITTER_STATE : 0 |
>
> Apart from VBT, this also depends on the Panel DPCD 71h.
> If bit 0 of 71h is 0, we may need Link training to exit PSR,
> If main link is off.
>
> So, unless we try it out on various panels and
> are confident about it, I suggest we keep this
> TRANSMITTER_STATE to 1.
>
> Thanks,
> Durga
>
>>                  VLV_EDP_PSR_ENABLE);
>> }
>>
>>--
>>2.1.0
>>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br