[Intel-gfx] [PATCH v2] drm/i915: Insert a command barrier on BLT/BSD cache flushes

[shuang.he at intel.com]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
Task id: 5626
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  353/353              353/353
ILK                                  353/353              353/353
SNB              +1                 399/422              400/422
IVB              +1-1              486/487              486/487
BYT                                  296/296              296/296
HSW              +1                 507/508              508/508
BDW              +2                 399/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt_kms_flip_nonexisting-fb      NSPT(1, M35)PASS(2, M35)      PASS(1, M35)
*IVB  igt_gem_pwrite_pread_display-copy-performance      PASS(2, M21M4)      DMESG_WARN(1, M4)
 IVB  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(1, M21)PASS(1, M4)      PASS(1, M4)
 HSW  igt_gem_storedw_loop_blt      DMESG_WARN(2, M19M20)PASS(1, M20)      PASS(1, M20)
 BDW  igt_gem_pwrite_pread_display-pwrite-blt-gtt_mmap-performance      DMESG_WARN(2, M28)PASS(1, M30)      PASS(1, M28)
 BDW  igt_gem_pwrite_pread_uncached-pwrite-blt-gtt_mmap-performance      DMESG_WARN(1, M28)PASS(1, M28)      PASS(1, M28)
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