[Intel-gfx] [PATCH 4/4] drm/i915: Use intel_gpu_freq() and intel_freq_opcode()

shuang.he at intel.com shuang.he at intel.com
Tue Jan 27 16:39:03 PST 2015


Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
Task id: 5641
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -1              353/353              352/353
ILK                                  353/353              353/353
SNB              +1-1              400/422              400/422
IVB              +2-1              485/487              486/487
BYT                                  296/296              296/296
HSW              +1-1              507/508              507/508
BDW                                  401/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gen3_render_linear_blits      PASS(3, M25M23)      CRASH(1, M23)
*SNB  igt_kms_flip_event_leak      NSPT(3, M35M22)      PASS(1, M22)
*SNB  igt_kms_flip_tiling_flip-changes-tiling      PASS(2, M35M22)      FAIL(1, M22)
 IVB  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(2, M34)PASS(3, M4)      PASS(1, M4)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(2, M34M4)PASS(5, M34M4M21)      PASS(1, M4)
*IVB  igt_gem_storedw_batches_loop_secure-dispatch      PASS(2, M34M4)      DMESG_WARN(1, M4)
 HSW  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(1, M40)PASS(5, M40M20)      PASS(1, M20)
 HSW  igt_gem_storedw_loop_vebox      DMESG_WARN(1, M20)PASS(2, M40M20)      DMESG_WARN(1, M20)
Note: You need to pay more attention to line start with '*'


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