[Intel-gfx] [PATCH v4 1/2] i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal()

[Chris Wilson]

On Thu, Jul 02, 2015 at 02:44:10PM -0700, Anuj Phogat wrote:
> In case of YF/YS tiled buffers libdrm need not know about the tiling
> format because these buffers don't have hardware support to be tiled
> or detiled through a fenced region. But, libdrm still need to know
> about buffer alignment restrictions because kernel uses it when
> resolving the relocation.
> 
> Mesa uses drm_intel_gem_bo_alloc_for_render() to allocate Yf/Ys buffers.
> So, use the passed alignment value in this function to initialize the
> align variable in drm_intel_bo. Note that we continue ignoring the
> alignment value passed to drm_intel_gem_bo_alloc() to follow the
> previous behavior.
> 
> V2: Add a condition to avoid allocation from cache. (Ben)
> V3: Make no changes in cache allocation strategy. Just update the alignment.
>     Update the aperture size estimate including the alignment. (Ben, Chris)
> V4: Move aperture size adjustments inside drm_intel_bo_gem_set_in_aperture_size()
>     Don't split sentences across the one-line header and the changelog. (Chris)
> 
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> Cc: Ben Widawsky <ben at bwidawsk.net>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>

We have pending issues with not being 48bit safe, but I don't think this
patch makes matters worse.

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre