[Intel-gfx] [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider

[Daniel Vetter]

On Mon, Jul 06, 2015 at 11:32:47AM +0200, Daniel Vetter wrote:
> On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
> > > Ville noticed that the PLL HW readout code parsed the fractional
> > > divider value as if the fractional divider was always enabled. This may
> > > result in a port clock state check mismatch if the preceeding modeset
> > > disabled the fractional divider, but left a non-zero divider value in
> > > the register.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Queued for -fixes (with cc: stable), thanks for the patch.

Maybe doesn't justify stable, so dropped that again.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch