[Intel-gfx] [PATCH 00/15] drm/i915: CHV DPIO power gating, take two

[Deepak]

On Thursday 09 July 2015 02:15 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Here's the new version of the CHV DPIO powergating feature. In short,
> it allows us to power off unused lanes in the display PHY. So should
> save some power when stuff is either disabled, or when running DP links
> with less than four lanes.
>
> My previous attempt [1] failed to actually enable the dynamic powerdown
> bits in the PHY, which meant it basically did nothing. Actually setting
> those bits has a pretty big effect on the hardware as CMN/TX/PCS
> registers stop working in powered down lanes. So dealing with that fact,
> and several nasty corner cases makes things a bit tricky in places.
>
> The series depends on my earlier DP pipe config cleanup [2] since we now
> depend on knowing which lanes are actually powered on when
> enabling/disabling DP ports.
>
> The entire thing is availabe from my github repo [3] where it's
> sitting on a few other patches, including my earlier DPLL cleanup
> series [4]. However there should be no real dependency on this other
> stuff apart from the already mentioned DP pipe config patches (which are
> also included in the branch).
>
> Deepak, perchance you would be willing to review this since you already
> reviwed my first attempt (and shot it full of holes)?

Sure. I will review the patches :)

> Oh, and the first two patches aren't really about DPIO powergating. But
> I wanted to get them out and one of them does touch the same code so
> I figured I'd sneak them in.
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-April/064403.html
> [2] http://lists.freedesktop.org/archives/intel-gfx/2015-July/070780.html
> [3] git://github.com/vsyrjala/linux.git chv_dpio_powergating_4
> [4] http://lists.freedesktop.org/archives/intel-gfx/2015-June/070036.html
>
> Ville Syrjälä (15):
>    drm/i915: Always program m2 fractional value on CHV
>    drm/i915: Always program unique transition scale for CHV
>    drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock
>      buffer disables there
>    drm/i915: Move DPIO port init earlier
>    drm/i915: Add locking around chv_phy_control_init()
>    drm/i915: Move VLV/CHV prepare_pll later
>    drm/i915: Add vlv_dport_to_phy()
>    drm/i915: Implement PHY lane power gating for CHV
>    drm/i915: Trick CL2 into life on CHV when using pipe B with port B
>    drm/i915: Force common lane on for the PPS kick on CHV
>    drm/i915: Enable DPIO SUS clock gating on CHV
>    drm/i915: Force CL2 off in CHV x1 PHY
>    drm/i915: Clean up CHV lane soft reset programming
>    drm/i915: Add some CHV DPIO lane power state asserts
>    drm/i915: Add CHV PHY LDO power sanity checks
>
>   drivers/gpu/drm/i915/i915_dma.c         |  20 ++
>   drivers/gpu/drm/i915/i915_reg.h         |  23 +++
>   drivers/gpu/drm/i915/intel_display.c    |  54 +----
>   drivers/gpu/drm/i915/intel_dp.c         | 315 +++++++++++++++++++----------
>   drivers/gpu/drm/i915/intel_drv.h        |  26 ++-
>   drivers/gpu/drm/i915/intel_hdmi.c       | 171 +++++++++++-----
>   drivers/gpu/drm/i915/intel_runtime_pm.c | 344 +++++++++++++++++++++++++++++---
>   7 files changed, 721 insertions(+), 232 deletions(-)
>