[Intel-gfx] [PATCH 4/6] drm/i915: set ILK_DPFC_FENCE_YOFF to 0 on SNB

[Ville Syrjälä]

On Thu, Jul 09, 2015 at 02:31:15PM -0300, Paulo Zanoni wrote:
> 2015-07-09 14:22 GMT-03:00 Ville Syrjälä <ville.syrjala at linux.intel.com>:
> > On Thu, Jul 09, 2015 at 07:10:04PM +0200, Daniel Vetter wrote:
> >> On Wed, Jul 08, 2015 at 05:58:57PM -0300, Paulo Zanoni wrote:
> >> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> >> >
> >> > The doc is pretty clear that this register should be set to 0 on SNB.
> >> > We already write y_offset to DPFC_CPU_FENCE_OFFSET a few lines below.
> >> >
> >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> >>
> >> Hm, do we have testcases where we have a sufficiently big y offset? We can
> >> just allocate 128 lines more and use that as the offset, that should be
> >> big enough everywhere. Actually make that 129 lines to check the tile-size
> >> rounding ;-)
> >>
> >> Ofc this means we need to have two sets of testcases for all the affected
> >> tests (i.e. everything that tries to test the gtt hw tracking).
> >>
> >> Another funny corner case (which we're getting wrong on skl even without
> >> fbc) is x offsets > 2048 pixels (since x/y offset registers don't hold
> >> bigger values and then it wraps).
> >>
> >> I.e. I'd like this patch (and the others) to be augmented with a Testcase:
> >> tag.
> >
> > I think the entire Y offset thing is currently being misprogrammed.
> > IIRC the offset is from the display base address but we program in
> > the offset from the start of the FB.
> 
> After patch 3, all the current tests pass on BDW. Can you suggest a
> different test that won't pass?

Ah patch 3 tries to fix it. It's not entirely accurate though since it
simply relies on an implementation detail of intel_gen4_compute_page_offset().
Well, assuming my recollection of the hardware details is correct.

Also IIRC intel_gen4_compute_page_offset() isn't even used on SKL/BXT
currently, so it should fail on those platforms.

-- 
Ville Syrjälä
Intel OTC